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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | C8051F015 |
| 寤犲晢锛� | Silicon Laboratories Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 24/171闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC 8051 MCU 32K FLASH 64TQFP |
| 妯欐簴鍖呰锛� | 160 |
| 绯诲垪锛� | C8051F01x |
| 鏍稿績铏曠悊鍣細 | 8051 |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 25MHz |
| 閫ｉ€氭€э細 | SMBus锛�2 绶�/I²C锛�锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 32 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 32KB锛�32K x 8锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| RAM 瀹归噺锛� | 2.25K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x10b; D/A 2x12b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 64-TQFP |
| 鍖呰锛� | 鎵樼洡 |
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.1.
CIP-51
TM CPU
1.1.1.
Fully 8051 Compatible
The C8051F000 family utilizes Silicon Laboratories鈥� proprietary CIP-51 microcontroller core. The CIP-51 is fully
compatible with the MCS-51
TM instruction set. Standard 803x/805x assemblers and compilers can be used to
develop software.
The core has all the peripherals included with a standard 8052, including four 16-bit
counter/timers, a full-duplex UART, 256 bytes of internal RAM space, 128 byte Special Function Register (SFR)
address space, and four byte-wide I/O Ports.
1.1.2.
Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute with a maximum system clock of 12-to-24MHz.
By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with only four instructions taking more than four system clock
cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to execute
them is as follows:
Instructions
26
50
5
14
7
3
1
2
1
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
With the CIP-51鈥檚 maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.4 shows a
comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.
Figure 1.4. Comparison of Peak MCU Execution Speeds
5
10
15
20
ADuC812
8051
(16MHz
clk)
Philips
80C51
(33MHz
clk)
Microchip
PIC17C75x
(33MHz
clk)
Silicon Labs
CIP-51
(25MHz clk)
MIPS
25
Rev. 1.7
12
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| C8051F236 | IC 8051 MCU 8K FLASH 48TQFP |
| PIC14000-04I/SP | IC MCU OTP 4KX14 A/D 28DIP |
| C8051F231 | IC 8051 MCU 8K FLASH 32LQFP |
| C8051F230 | IC 8051 MCU 8K FLASH 48TQFP |
| C8051F226 | IC 8051 MCU 8K FLASH 48TQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| C8051F015DK | 鍔熻兘鎻忚堪:闁嬬櫦(f膩)鏉垮拰宸ュ叿鍖� - 8051 Dev Kit for F015-19 RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鐢�(ch菐n)鍝�:Development Kits 宸ュ叿鐢ㄤ簬瑭曚及:C8051F960, Si7005 鏍稿績: 鎺ュ彛椤炲瀷:USB 宸ヤ綔闆绘簮闆诲: |
| C8051F015-GQ | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 10ADC 64P MCU RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| C8051F015-GQR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 10ADC 64Pin MCU Tape and Reel RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| C8051F015R | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU C +-10Bit 64Pin RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| C8051F015TB | 鍔熻兘鎻忚堪:闁嬬櫦(f膩)鏉垮拰宸ュ叿鍖� - 8051 USE 634-C8051F005TB RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鐢�(ch菐n)鍝�:Development Kits 宸ュ叿鐢ㄤ簬瑭曚及:C8051F960, Si7005 鏍稿績: 鎺ュ彛椤炲瀷:USB 宸ヤ綔闆绘簮闆诲: |
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