參數(shù)資料
型號： C8051F015-TB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 67/171頁
文件大?。?/td> 0K
描述： BOARD PROTOTYPING W/C8051F015
標(biāo)準(zhǔn)包裝： 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20.2.
PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of
the 16-bit counter/timer and PCA0L is the low byte (LSB).
Reading PCA0L automatically latches the value of
PCA0H at the same time. By reading the PCA0L Register first, this allows the PCA0H value to be held (at the time
PCA0L was read) until the user reads the PCA0H Register. Reading PCA0H or PCA0L does not disturb the
counter operation. The CPS1 and CPS0 bits in the PCA0MD register select the timebase for the counter/timer as
shown in Table 20.2.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to
logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1
enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software. (Note: PCA0 interrupts must be
globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit
(IE.7) and the EPCA0 bit in EIE1 to logic 1.) Clearing the CIDL bit in the PCA0MD register allows the PCA to
continue normal operation while the microcontroller core is in Idle mode.
Table 20.2. PCA Timebase Input Options
CPS1
CPS0
Timebase
0
System clock divided by 12
0
1
System clock divided by 4
1
0
Timer 0 overflow
1
High-to-low transitions on ECI (max rate = system clock divided by 4)
Figure 20.7. PCA Counter/Timer Block Diagram
PCA0H
PCA0L
PCA0CN
C
F
C
R
C
F
0
C
F
2
C
F
1
C
F
4
C
F
3
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
00
01
10
11
PCA0MD
C
I
D
L
E
C
F
C
P
S
1
C
P
S
0
Snapshot
Register
To SFR Bus
Overflow
To PCA Interrupt System
IDLE
0
1
CF
PCA0L
read or
write
To PCA Modules
159
Rev. 1.7
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