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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� C8051F012R
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋佹暩(sh霉)锛� 39/171闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC 8051 MCU 32K FLASH 32LQFP
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绯诲垪锛� C8051F01x
鏍稿績铏曠悊鍣細 8051
鑺珨灏哄锛� 8-浣�
閫熷害锛� 20MHz
閫ｉ€氭€э細 SMBus锛�2 绶�/I²C锛夛紝SPI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 8
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 32KB锛�32K x 8锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 256 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 3.6 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 4x10b; D/A 2x12b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 32-LQFP
鍖呰锛� 鍓垏甯� (CT)
鍏跺畠鍚嶇ū锛� 336-1007-1
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
The Timer 2 overflow rate, when in Baud Rate Generator Mode and using an internal clock source, is determined
solely by the Timer 2 16-bit reload value (RCAP2H:RCAP2L). The Timer 2 clock source is fixed at SYSCLK/2.
The Timer 2 overflow rate can be calculated as follows:
T2_OVERFLOWRATE = (SYSCLK/2) / (65536 鈥� [RCAP2H:RCAP2L]).
Timer 2 can be selected as the baud rate generator for RX and/or TX by setting RCLK (T2CON.5) and/or TCLK
(T2CON.4), respectively. When either RCLK or TCLK is set to logic 1, Timer 2 interrupts are automatically
disabled and the timer is forced into Baud Rate Generator Mode with SYSCLK/2 as its clock source. If a different
timebase is required, setting the C/T2 bit (T2CON.1) to logic 1 will allow Timer 2 to be clocked from the external
input pin T2. See the Timers section for complete timer configuration details.
Figure 18.5. UART Modes 1, 2, and 3 Interconnect Diagram
OR
RS-232
C8051Fxxx
RS-232
LEVEL
XLTR
TX
RX
C8051Fxxx
RX
TX
MCU
RX
TX
133
Rev. 1.7
鐩搁棞(gu膩n)PDF璩囨枡
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