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Advanced
Information
6.6.
Interrupt Sources
The DMA contains multiple interrupt sources. Some of these can be individually enabled to generate interrupts as
necessary. The DMA Control Register (DMA0CN, Figure 6.4) and DMA Configuration Register (DMA0CF,
Figure 6.5) contain the enable bits and flags for the DMA interrupt sources. When an interrupt is enabled and the
interrupt condition occurs, a DMA interrupt will be generated (EIE2.7 is set to ‘1’).
The DMA flags that can generate a DMA0 interrupt are:
1.
completed, and the DMA interface is idle.
2.
ADC1 Data Overflow Error (DMA0CN.4, DMA0DE1) occurs when the DMA interface cannot access
XRAM for two conversion cycles of ADC1. This flag indicates that at least one conversion result from
ADC1 has been discarded.
3.
ADC0 Data Overflow Error (DMA0CN.3, DMA0DE0) occurs when the DMA interface cannot access
XRAM for two conversion cycles of ADC0. This flag indicates that at least one conversion result from
ADC0 has been discarded.
4.
ADC1 Data Overflow Warning (DMA0CN.1, DMA0DO1) occurs when data from ADC0 becomes
available and the DMA has not yet written the previous results to XRAM. This interrupt source can be
enabled and disabled with the Data Overflow Warning Enable bit (DMA0CN.2, DMA0DOE).
5.
ADC0 Data Overflow Warning (DMA0CN.0, DMA0DO0) occurs when data from ADC1 becomes
available and the DMA has not yet written the previous results to XRAM. This interrupt source can be
enabled and disabled with the Data Overflow Warning Enable bit (DMA0CN.2, DMA0DOE).
6.
Repeat Counter Overflow (DMA0CF.2, DMA0CI) occurs when the Repeat Counter reaches the Repeat
Counter Limit. This interrupt source can be enabled and disabled with the Repeat Counter Overflow Inter-
rupt Enable bit (DMA0CF.3, DMA0CIE).
7.
End Of Operation (DMA0CF.0, DMA0EO) occurs when an End Of Operation instruction is reached in
the Instruction Buffer. This interrupt source can be enabled and disabled with the End Of Operation Interrupt
Enable bit (DMA0CF.1, DMA0EOE).
DMA Operations Complete (DMA0CN.6, DMA0INT) occurs when all DMA operations have been
6.7.
Data Buffer Overflow Warnings and Errors
The data paths from the ADCs to XRAM are double-buffered when using the DMA interface. When a conversion is
completed by the ADC, it first enters the ADCs data register. If the DMA’s data buffer is empty, the conversion
results will immediately be written into the DMA’s internal data buffer for that ADC. Data in the DMA’s internal data
buffer is written to XRAM at the first available opportunity (see
Section “6.3. XRAM Addressing and Setup” on
page 72
). Conversion results from the ADC’s data registers are not copied into the DMA’s data buffer until data in the
buffer has been written to XRAM. When a conversion is completed and the DMA’s data buffer is not empty, an over-
flow warning flag is generated. If a second conversion data word becomes available before the DMA’s data buffer is
written to XRAM, the data in the ADC’s data registers is over-written with the new data word, and a data overflow
error flag is generated.