參數資料
型號： C8051F011
廠商： Cygnal Technologies
英文描述： 20 MIPS,32k Flash,256 Ram,10bit ADC,48 Pin MCU(20 MIPS,32k 閃速存儲器,256 Ram,10位 ADC,48 腳 MCU)
中文描述： 20 MIPS的，32K閃存，256羊，10位ADC，48引腳微控制器（20 MIPS的，32K的閃速存儲器，256，羊，10位ADC和48腳微控制器）
文件頁數： 114/170頁
文件大?。?/td> 1294K
代理商： C8051F011
Page 114
CYGNAL Integrated Products, Inc.
2001
4.2001; Rev. 1.3
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
PRELIMINARY
16.2.
A typical SMBus transaction consists of a START condition, followed by an address byte, one or more bytes of data,
and a STOP condition. The address byte and each of the data bytes are followed by an ACKNOWLEDGE bit from
the receiver. The address byte consists of a 7-bit address plus a direction bit. The direction bit (R/W) occupies the
least-significant bit position of the address. The direction bit is set to logic 1 to indicate a “READ” operation and
cleared to logic 0 to indicate a “WRITE” operation. A general call address (0x00 +R/W) is recognized by all slave
devices allowing a master to address multiple slave devices simultaneously.
All transactions are initiated by the master, with one or more addressed slave devices as the target. The master
generates the START condition and then transmits the address and direction bit. If the transaction is a WRITE
operation from the master to the slave, the master transmits the data a byte at a time waiting for an
ACKNOWLEDGE from the slave at the end of each byte. If it is a READ operation, the slave transmits the data
waiting for an ACKNOWLEDGE from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 16.3 illustrates a typical SMBus
transaction.
Operation
Figure 16.3. SMBus Transaction
The SMBus interface may be configured to operate as either a master or a slave. At any particular time, it will be
operating in one of the following four modes:
16.2.1. Master Transmitter Mode
Serial data is transmitted on SDA while the serial clock is output on SCL. The first byte transmitted contains the
address of the target slave device and the data direction bit. In this case the data direction bit (R/W) will be logic 0
to indicate a “WRITE” operation. The master then transmits one or more bytes of serial data. After each byte is
transmitted, an acknowledge bit is generated by the slave. To indicate the beginning and the end of the serial
transfer, the master device outputs START and STOP conditions.
16.2.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The first byte is transmitted by the master and
contains the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be
logic 1 to indicate a “READ” operation. Serial data is then received from the slave on SDA while the master
outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, an
acknowledge bit is transmitted by the master. The master outputs START and STOP conditions to indicate the
beginning and end of the serial transfer.
16.2.3. Slave Transmitter Mode
Serial data is transmitted on SDA while the serial clock is received on SCL. First, a byte is received that contains an
address and data direction bit. In this case the data direction bit (R/W) will be logic 1 to indicate a “READ”
operation. If the received address matches the slave’s assigned address (or a general call address is received) one or
more bytes of serial data are transmitted to the master. After each byte is received, an acknowledge bit is transmitted
by the master. The master outputs START and STOP conditions to indicate the beginning and end of the serial
transfer.
START
SLAVE ADDR R/W
ACK
DATA
ACK
NACK
STOP
DATA
Time
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PDF描述
C8051F012 20 MIPS,32k Flash,256 Ram,10bit ADC,32 Pin MCU(20 MIPS,32k 閃速存儲器,256 Ram,10位 ADC,32 腳 MCU)
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C8051F006 25 MIPS,32k Flash,2.25k Ram,12bit ADC,48 Pin MCU(25 MIPS,32k 閃速存儲器,2.25k Ram,12位 ADC,48 腳 MCU)
相關代理商/技術參數
參數描述
C8051F011-GQ 功能描述:8位微控制器 -MCU 32KB 10ADC 48P MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F011-GQR 功能描述:8位微控制器 -MCU 32KB 10ADC 48Pin MCU Tape and Reel RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F011R 功能描述:8位微控制器 -MCU C 10Bit 48Pin RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F012 功能描述:8位微控制器 -MCU 32KB 10ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
C8051F012/005 制造商:Silicon Laboratories Inc 功能描述:
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