參數(shù)資料
型號： C8051F010-TB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 74/171頁
文件大?。?/td> 0K
描述： BOARD PROTOTYPING W/C8051F010
標準包裝： 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
21.1.
Boundary Scan
The Data Register in the Boundary Scan path is an 87-bit shift register. The Boundary DR provides control and
observability of all the device pins as well as the SFR bus and Weak Pullup feature via the EXTEST and SAMPLE
commands.
Table 21.1. Boundary Data Register Bit Definitions
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
Bit
Action
Target
Capture
Reset Enable from MCU
0
Update
Reset Enable to /RST pin
Capture
Reset input from /RST pin
1
Update
Reset output to /RST pin
Capture
External Clock from XTAL1 pin
2
Update
Not used
Capture
Weak pullup enable from MCU
3
Update
Weak pullup enable to Port Pins
Capture
SFR Address Bus bit from CIP-51 (e.g. Bit4=SFRA0, Bit5=SFRA1…)
4-11
Update
SFR Address Bus bit to SFR Address Bus (e.g. Bit4=XSFRA0, Bit5=XSFRA1)
Capture
SFR Data Bus bit read from SFR (e.g. Bit12=SFRD0, Bit13=SFRD1…)
12-19
Update
SFR Data Bus bit written to SFR (e.g. Bit12=SFRD0, Bit13=SFRD1…)
Capture
SFR Write Strobe from CIP-51
20
Update
SFR Write Strobe to SFR Bus
Capture
SFR Read Strobe from CIP-51
21
Update
SFR Read Strobe to SFR Bus
Capture
SFR Read/Modify/Write Strobe from CIP-51
22
Update
SFR Read/Modify/Write Strobe to SFR Bus
Capture
P0.n output enable from MCU (e.g. Bit23=P0.0, Bit25=P0.1, etc.)
23,25,27,29,
31,33,35,37
Update
P0.n output enable to pin (e.g. Bit23=P0.0oe, Bit25=P0.1oe, etc.)
Capture
P0.n input from pin (e.g. Bit24=P0.0, Bit26=P0.1, etc.)
24,26,28,30,
32,34,36,38
Update
P0.n output to pin (e.g. Bit24=P0.0, Bit26=P0.1, etc.)
Capture
P1.n output enable from MCU (e.g. Bit39=P1.0, Bit41=P1.1, etc.)
39,41,43,45,
47,49,51,53
Update
P1.n output enable to pin (e.g. Bit39=P1.0oe, Bit41=P1.1oe, etc.)
Capture
P1.n input from pin (e.g. Bit40=P1.0, Bit42=P1.1, etc.)
40,42,44,46,
48,50,52,54
Update
P1.n output to pin (e.g. Bit40=P1.0, Bit42=P1.1, etc.)
Capture
P2.n output enable from MCU (e.g. Bit55=P2.0, Bit57=P2.1, etc.)
55,57,59,61,
63,65,67,69
Update
P2.n output enable to pin (e.g. Bit55=P2.0oe, Bit57=P2.1oe, etc.)
Capture
P2.n input from pin (e.g. Bit56=P2.0, Bit58=P2.1, etc.)
56,58,60,62,
64,66,68,70
Update
P2.n output to pin (e.g. Bit56=P2.0, Bit58=P2.1, etc.)
Capture
P3.n output enable from MCU (e.g. Bit71=P3.0, Bit73=P3.1, etc.)
71,73,75,77,
79,81,83,85
Update
P3.n output enable to pin (e.g. Bit71=P3.0oe, Bit73=P3.1oe, etc.)
Capture
P3.n input from pin (e.g. Bit72=P3.0, Bit74=P3.1, etc.)
72,74,76,78,
80,82,84,86
Update
P3.n output to pin (e.g. Bit72=P3.0, Bit74=P3.1, etc.)
165
Rev. 1.7
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