參數(shù)資料
型號: C8051F006R
廠商: Silicon Laboratories Inc
文件頁數(shù): 136/171頁
文件大小: 0K
描述: IC 8051 MCU 32K FLASH 48TQFP
標(biāo)準(zhǔn)包裝: 1
系列: C8051F00x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1004-1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
67
Rev. 1.7
Mnemonic
Description
Bytes
Clock
Cycles
ACALL addr11
Absolute subroutine call
2
3
LCALL addr16
Long subroutine call
3
4
RET
Return from subroutine
1
5
RETI
Return from interrupt
1
5
AJMP addr11
Absolute jump
2
3
LJMP addr16
Long jump
3
4
SJMP rel
Short jump (relative address)
2
3
JMP @A+DPTR
Jump indirect relative to DPTR
1
3
JZ rel
Jump if A equals zero
2
2/3
JNZ rel
Jump if A does not equal zero
2
2/3
CJNE A,direct,rel
Compare direct byte to A and jump if not equal
3
3/4
CJNE A,#data,rel
Compare immediate to A and jump if not equal
3
3/4
CJNE Rn,#data,rel
Compare immediate to register and jump if not
equal
3
3/4
CJNE @Ri,#data,rel
Compare immediate to indirect and jump if not
equal
3
4/5
DJNZ Rn,rel
Decrement register and jump if not zero
2
2/3
DJNZ direct,rel
Decrement direct byte and jump if not zero
3
3/4
NOP
No operation
1
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through register R0-R1
rel - 8-bit, signed (two’s compliment) offset relative to the first byte of the following instruction. Used by SJMP
and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00-0x7F) or an
SFR (0x80-0xFF).
#data - 8-bit constant
#data 16 - 16-bit constant
bit - Direct-addressed bit in Data RAM or SFR.
addr 11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-
byte page of program memory as the first byte of the following instruction.
addr 16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the
64K-byte program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted Intel Corporation 1980.
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