參數(shù)資料
型號: C8051F005-GQR
廠商: Silicon Laboratories Inc
文件頁數(shù): 29/171頁
文件大小: 0K
描述: IC 8051 MCU 32K FLASH 64TQFP TAP
產(chǎn)品培訓(xùn)模塊: Serial Communication Overview
標準包裝: 500
系列: C8051F00x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 帶卷 (TR)
配用: 336-1188-ND - DEV KIT FOR F005/006/007
其它名稱: 977.000
Q2567667
Q2910019
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 17.2. Typical SPI Interconnection
Master
Device
MOSI
Slave
Device
NSS
Slave
Device
NSS
Slave
Device
MISO
SCK
Port
I/O
NSS
VDD
Port
I/O
Port
I/O
17.1.
Signal Descriptions
The four signals used by the SPI (MOSI, MISO, SCK, NSS) are described below.
17.1.1. Master Out, Slave In
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to
serially transfer data from the master to the slave. Data is transferred most-significant bit first.
17.1.2. Master In, Slave Out
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used
to serially transfer data from the slave to the master.
Data is transferred most-significant bit first. A SPI slave
places the MISO pin in a high-impedance state when the slave is not selected.
17.1.3. Serial Clock
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to
synchronize the transfer of data between the master and slave on the MOSI and MISO lines.
17.1.4. Slave Select
The slave select (NSS) signal is an input used to select the SPI module when in slave mode by a master, or to
disable the SPI module when in master mode. When in slave mode, it is pulled low to initiate a data transfer and
remains low for the duration of the transfer.
Rev. 1.7
124
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