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參數(shù)資料
| 型號： | C3017 |
| 廠商： | IMP INC. |
| 英文描述： | 10 Volt Analog Mixed Mode |
| 中文描述： | 10伏模擬混合模式 |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 39K |
| 代理商： | C3017 |
92
C3017-4-98
Process C3017
Starting Material
Starting Mat. Resistivity
Typ. Operating Voltage
Well Type
Metal Layers
Poly Layers
Contact Size
Via Size
Metal-1 Width/Space
Metal-2 Width/Space
Gate Poly Width/Space
P <100>
15 - 25
-cm
10V
P-well
2
2
2.0x2.0
μ
m
2.0x2.0
μ
m
3.5 / 2.5
μ
m
5.0 / 3.0
μ
m
4.0 / 2.5
μ
m
N+/P+ Width/Space
N+ To P+ Space
Contact To Poly Space
Contact Overlap Of Diffusion
Contact Overlap Of Poly
Metal-1 Overlap Of Contact
Metal-1 Overlap Of Via
Metal-2 Overlap Of Via
Minimum Pad Opening
Minimum Pad-to-Pad Spacing
Minimum Pad Pitch
3.0 / 3.0
μ
m
12
μ
m
2.5
μ
m
1.5
μ
m
1.0
μ
m
1.0
μ
m
1.75
μ
m
1.5
μ
m
100x100
μ
m
5.0
μ
m
80.0
μ
m
Special Feature of C3017 Process: P-well analog process with double metal CMOS 3.0
μ
m
technology.
Physical Characteristics
5
4
3
2
1
00
1
2
3
4
5
6
7
8
9
10
ID vsVD, W/L = 20/4.0
Drain Voltage (v) V
DS
n-ch Transistor IV characteristics of a 20/4.0 device
D
D
VGS = 10V
VGS = 9.0V
VGS = 8.0V
VGS = 7.0V
VGS = 6.0V
VGS = 5.0V
VGS = 4.0V
VGS = 3.0V
VGS = 2.0V
-3
-2.5
-2
-1.5
-1
-.5
00
1
2
3
4
5
6
7
8
9
10
ID vsVD, W/L = 20/4.0
Drain Voltage (v) V
DS
p-ch Transistor IV characteristics of a 20/4.0 device
D
D
VGS = -10V
VGS = -9.0V
VGS = -8.0V
VGS = -7.0V
VGS = -6.0V
VGS = -5.0V
VGS = -4.0V
VGS = -3.0V
VGS = -2.0V
Cross-sectional view of the C3017 process
Second metal
SIO
2
LTO
p
+
p
+
p
+
n
+
p
Field Oxide
p
D
Poly gate
p-well
s
D
S
N
–
B
C
P
VIA
Metal 1
N
+
substrate
n
+
n
+
A1
p
p
SIO
2
n-epi
S
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