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參數(shù)資料
| 型號： | C0603C103F2RC |
| 廠商： | KEMET Corporation |
| 英文描述： | CERAMIC CHIP CAPACITORS |
| 中文描述： | 陶瓷芯片電容器 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 1023K |
| 代理商： | C0603C103F2RC |
KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
20
°
20
°
Maximum
Typical
Punched Carrier (Paper Tape) Configuration (Ceramic Chips Only):
Table 1: 8 & 12mm Punched Tape
(
Metric Dimensions Will Govern)
Variable Dimensions - Millimeters (Inches)
Note:
1. A0, B0 and T determined by the maximum dimensions to the ends of the terminals extending from the
body and/or the body dimensions of the component. The clearance between the ends of the terminals or
body of the component to the sides and depth of the cavity (A0, B0 and T) must be within 0.05mm (.002)
minimum and 0.50mm (.020) maximum. The clearance allowed must also prevent rotation of the component
within the cavity of not more than 20 degrees (see sketches A and B).
2. Tape with components shall pass around radius "R" without damage.
3. KEMET nominal thicknesses are: 0402 = 0.6mm and all others 0.95mm minimum.
8mm
and
12mm
1.5
+0.10, -0.0
(.059
+0.004, -0.0)
1.75
±
0.10
(.069
±
0.004)
4.0
±
0.10
(.157
±
0.004)
2.0
±
0.05
(.079
±
0.002)
0.10
(.004)
Max.
0.75
(.030)
Min.
0.75
(.030)
Min.
25 (.984)
See Note 2
Table 1
Tape
Size
D
0
P
0
E
P
2
T
1
G
1
G
2
R Min.
8mm
1/2
Pitch
2.0
±
0.10
(.079
±
.004)
See Require-
ments
Section 3.3 (d)
4.0
±
0.10
(0.157
±
.004)
3.5
±
0.05
(.138
±
.002)
8.0
±
0.3
(.315
±
0.012)
See Note 1
Table 1
1.1mm (.043)
Max. for Paper
Base Tape and
1.6mm (.063)
Max. for Non-
Paper Base
Compositions.
See Note 3.
Tape
Size
P
1
W
F
A
0
B
0
T
8mm
12mm
4.0
±
0.10
(0.157
±
.004)
8.0
±
0.10
(0.315
±
.004)
12mm
Double
Pitch
12.0
±
0.3
(.472
±
.012)
5.5
±
0.05
(.217
±
.002)
Table 1: 8 & 12mm Punched Tape
(
Metric Dimensions Will Govern)
Constant Dimensions - Millimeters (Inches)
Sketch B:
Max. Component
Rotation - Front
Cross Sectional View
Sketch C:
Component Rotation - Top View
A
0
B
0
P
1
P
0
P
2
D
0
F
E
W
Center lines
of cavity
10 pitches cumulative
tolerance on tape
±
0.2 (
±
0.008)
Top
Tape
Cover
T
User Direction of Feed
T
1
Max. Cavity Size
See Note 1
Table 1
Bottom
Tape
Cover
G
2
R
Sketch A:
Bending Radius
See Note 2
Table 1
CERAMIC CHIP CAPACITORS
Packaging Information
96
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| C0603C103F3GAC | 功能描述:多層陶瓷電容器MLCC - SMD/SMT .010UF 25.0V RoHS:否 制造商:American Technical Ceramics (ATC) 電容:10 pF 容差:1 % 電壓額定值:250 V 溫度系數(shù)/代碼:C0G (NP0) 外殼代碼 - in:0505 外殼代碼 - mm:1414 工作溫度范圍:- 55 C to + 125 C 產(chǎn)品:Low ESR MLCCs 封裝:Reel |
| C0603C103F3GAC7867 | 功能描述:多層陶瓷電容器MLCC - SMD/SMT .010UF 25.0V RoHS:否 制造商:American Technical Ceramics (ATC) 電容:10 pF 容差:1 % 電壓額定值:250 V 溫度系數(shù)/代碼:C0G (NP0) 外殼代碼 - in:0505 外殼代碼 - mm:1414 工作溫度范圍:- 55 C to + 125 C 產(chǎn)品:Low ESR MLCCs 封裝:Reel |
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