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參數(shù)資料
| 型號： | BW4104X |
| 英文描述： | Rad-hard dual J-K flip flop with preset and clear |
| 中文描述： | BW4104X LVDS接收器|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 7/7頁 |
| 文件大?。?/td> | 102K |
| 代理商： | BW4104X |
SEC ASIC
ANALOG
0.35um LVDS Receiver
BW4104X
Test Method
Following figures are LVDS receiver test methods. Low frequency test case is shown in Figure 1 and
high frequency test case is shown in Figure 2. For exampl, in low frequency test case LVDS input
data(RAP/N,RBP/N,etc) are input to receiver chip(Rx chip) at 65MHz, and Rx chip
outputs(RXOUT<0:6>,etc) at 20MHz.
Figure 1. Low Frequency Test Case
In high frequency test case, Transmitter chip(Tx Chip) is needed. For example, Test data input to Tx
chip at 65MHz,Rx chip is received LVDS data at 455MHz each channels. Test data and expectation
value using this test are made from slow frequency test result.
65MHz
output
65MHz
input
RAP
RAN
RBP
RBN
RCP
RCN
RDP
RDN
RCLKP
RCLKN
BW4104X
Tx Chip
RXOUT<0:6>
RXOUT<7:13>
RXOUT<14:20>
RXOUT<21:2
7>
CLKOUT
7
7
7
7
7
7
7
7
7
7
TA<0:6>
TB<0:6>
TC<0:6>
TD<0:6>
CLKIN
PDWNN
Figure 2. High Frequency Test Case
RAP
RAN
RBP
RBN
RCP
RCN
RDP
RDN
RCLKP
RCLKN
PDWNN
BW4104X
65MHz
input
20MHz
input
20MHz
output
RXOUT<0:6>
RXOUT<7:1
3>
RXOUT<14:2
0>
RXOUT<21:2
7>
CLKOUT
7
7
7
7
7
7 / 7
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