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參數(shù)資料
| 型號(hào)： | BW1249X |
| 英文描述： | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1249X 4-14位40MSPS單援BW1249X |數(shù)據(jù)資料 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 77K |
| 代理商： | BW1249X |
SEC ASIC
BW1244D
3.3V 10BIT 0.5MSPS DAC
ANALOG
CORE LAYOUT GUIDE
bw1244x
D[9]
EXTREF
VOUT
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
DACCON
V
V
V
V
V
V
V
V
Pin Name
Property
Pin Usage
Pin Layout Guide
D[9:0]
DI
Internal / External
1. Digital Input Signal lines must have same length to
reduce propagation delay.
DACCON
DI
Internal / External
PWDNB
DI
Internal / External
VRT
AB
External
1. Voltage reference lines (VRT and VRB) must be wide metal
to reduce voltage drop of metal lines.
2. VOUT signal should not be crossed by any signals and
should not run next to digital signals to minimize capacitive
coupling between the two signals.
VRB
AB
External
EXTREF
AI
Internal / External
VOUT
AO
Internal / External
VDDA
AP
External
1. It is recommended that you use thick analog power metal.
When connected to PAD, the path should be kept as short
as possible.
2. Digital power and analog power are separately used.
VSSA
AG
External
VDDD
DP
External
VSSD
DG
External
VBBA
AG
External
1. When
P+ active to remove the substrate and coupling noise.
In that case, the power metal should be connected to PAD directly.
2. The Bulk power is used to reduce the influence of substrate noise.
the core block is connected to other blocks, it must be double guard-ring using N-well and
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