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參數(shù)資料
| 型號： | BW1222L |
| 英文描述： | Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1222L AFE的用于CCD / CIS信號處理器|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 140K |
| 代理商： | BW1222L |
BW1223X
8BIT 40MSPS ADC
SEC ASIC
ANALOG
PACKAGE
PIN
DESCRIPTION
NAME
PIN NO.
I/O TYPE
PIN DESCRIPTION
VRT
1
AB
+2.6V External Reference Top Bias.
VRTS
2
AB
Internal Reference Top Bias.
(Short to VRTS for Self-Bias.)
VRBS
3
AB
Internal Reference Bottom Bias.
(Short to VRBS for Self-Bias.)
VRB
4
AB
+0.6V External Reference Bottom Bias.
NC
5
-
No Connection
VDDA
6, 7
AP
+3.3V Analog Power.
VBBA
8
AG
Analog Sub Bias.
VSSA
9, 10
AG
Analog Ground.
AIN
11
AI
Analog Input.
Input Span = VRT ~ VRB.
NC
12~17
-
No Connection
VDDP
18
DP
PAD Power
VSSP
19
DG
PAD Ground
CLK
20
DI
Clock Input.
NC
21~26
-
No Connection
DO[7:0]
34~27
DO
Digital Output.
NC
35~43
-
No Connection
VBBD
44
DG
Digital Sub Bias.
VSSD
45, 46
DG
Digital Ground.
VDDD
47, 48
DP
Digital Power.
I/O TYPE ABBR.
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
AP : Analog Power
DP : Digital Power
AG : Analog Ground
DG : Digital Ground
10 / 11
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