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參數(shù)資料
| 型號(hào)： | BW1221L |
| 英文描述： | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1221L 10位80Msps的雙DAC BW1221L |數(shù)據(jù)資料 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 140K |
| 代理商： | BW1221L |
BW1223X
8BIT 40MSPS ADC
SEC ASIC
ANALOG
CORE
EVALUATION
GUIDE
1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of
HOST DSP back-end circuit.
2. The reference voltages may be biased externally through VRT and VRB pins, otherwise these voltages
are internally generated with VRT and VRB shorted to VRTS and VRBS respectively.
M
B
A
M
D
F
H
C
A
V
V
C
D
D
D
D
D
D
D
D
V
V
b
2
T
R
0
B
R
G
G
V
V
V
V
G
+
A
G
+
:
N
:
8 / 11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BW1221L_2CLK | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| BW1221L_3CLK | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| BW1222L | Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs |
| BW1237X | Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state) with 3.6 V tolerant inputs and outputs |
| BW1238X | Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state) with 3.6 V tolerant inputs and outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BW1221L_2CLK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1221L_2CLK 10BIT|Data Sheet |
| BW1221L_3CLK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1221L_3CLK 10Bit 30MSPS TRIPLE DAC|Data Sheet |
| BW1222L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1222L AFE For CCD/CIS Signal Processor|Data Sheet |
| BW1223X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1223X 8Bit 40MSPS ADC BW1223X|Data Sheet |
| BW1224L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:BW1224L AFE for CCD/CIS Signal Processor BW1224L|Data Sheet |
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