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參數(shù)資料
| 型號： | BUF16820 |
| 英文描述： | 14-Channel GAMMA VOLTAGE GENERATOR with Programmable VCOM Outputs and OTP Memory |
| 中文描述： | 14通道伽瑪電壓發(fā)生器具有可編程威科姆輸出和OTP存儲器 |
| 文件頁數(shù)： | 7/30頁 |
| 文件大小： | 681K |
| 代理商： | BUF16820 |
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SBOS356A FEBRUARY 2006 REVISED OCTOBER 2006
www.ti.com
7
DATA RATES
The two-wire bus operates in one of three speed modes:
Standard—allows a clock frequency of up to 100kHz;
Fast—allows a clock frequency of up to 400kHz;
High-speed—allows a clock frequency of up to 3.4MHz.
The BUF16820 is fully compatible with all three modes. No
special action is required to use the device in Standard or
Fast modes, but High-speed (Hs) mode must be activated.
To activate Hs mode, send a special address byte of
00001
xxx
, with SCL = 400kHz, following the START
condition; where
xxx
are bits unique to the Hs-capable
master, which can be any value. This byte is called the Hs
master code. (Note that this is different from normal
address bytes—the low bit does not indicate read/write
status.) The BUF16820 will respond to the Hs command
regardless of the value of these last three bits. The
BUF16820 will not acknowledge this byte; the
communication protocol prohibits acknowledgement of
the Hs master code. Upon receiving a master code, the
BUF16820 will switch on its Hs mode filters, and
communicate at up to 3.4MHz. Additional high-speed
transfers may be initiated without resending the Hs mode
byte by generating a repeat START without a STOP. The
BUF16820 will switch out of Hs mode with the next STOP
condition.
GENERAL CALL RESET AND POWER-UP
The BUF16820 responds to a General Call Reset, which
is an address byte of 00h (0000 0000) followed by a data
byte of 06h (0000 0110). The BUF16820 acknowledges
both bytes. Upon receiving a General Call Reset, the
BUF16820 performs a full internal reset, as though it had
been powered off and then on. It always acknowledges the
General Call address byte of 00h (0000 0000), but does
not acknowledge any General Call data bytes other than
06h (0000 0110).
The BUF16820 automatically performs a reset upon
power-up. As part of the reset, the BUF16820 is configured
for all outputs to change either to the programmed OTP
memory values, or to 0000 if the OTP values have not been
programmed.
The BUF16820 resets all outputs to the OTP memory
values (or to 0000 if the OTP values have not been
programmed) when the device address is sent, followed
by a valid DAC address with bits D7 to D5 set to ‘100’. If
these bits are set to ‘010’, only the DAC being addressed
in this most significant byte and the following least
significant byte will be reset.
OUTPUT VOLTAGE
Buffer output values are determined by the reference
voltages (V
REFH
and V
REFL
) and the decimal value of the
binary input code used to program that buffer. The value is
calculated using Equation (1):
V
OUT
V
REFH
V
REFL
1024
Decimal Value of Code
V
REFL
The valid voltage ranges for the reference voltages are:
4V
V
REFH
V
S
0.2V and 0.2V
V
REFL
V
S
4V
The BUF16820 outputs are capable of a full-scale voltage
output change in typically 5
μ
s—no intermediate steps are
required.
OUTPUT LATCH
Updating the DAC register is not the same as updating the
DAC output voltage, because the BUF16820 features a
double-buffered register structure. There are three
methods for latching transferred data from the storage
registers into the DACs to update the DAC output
voltages.
Method 1 requires externally setting the latch pin (LD)
LOW, LD = LOW, which updates each DAC output
voltage whenever its corresponding register is updated.
Method 2 externally sets LD = HIGH to allow all DAC
output voltages to retain their values during data transfer
until LD = LOW, which then simultaneously updates the
output voltages of all DACs to the new register values. Use
this method to transfer a future data set in advance to
prepare for a very fast output voltage update.
Method 3 uses software control. LD is maintained HIGH,
and all DACs are updated when the master writes a ‘1’ in
bit 15 and a ‘0’ in bit 14 of any DAC register. The update
occurs after receiving the 16-bit data for the
currently-written register.
The General Call Reset or a reset upon power-up updates
the DAC regardless of the state of the latch pin.
(1)
(2)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BUF16820AIDAPR | 功能描述:LCD Gamma緩沖器 14-Ch Vltg Generator w/2 Prog VCOM Out RoHS:否 制造商:Maxim Integrated 輸入補償電壓: 轉(zhuǎn)換速度: 電源電壓-最大:20 V 電源電壓-最小:9 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:TQFN-38 封裝:Tube |
| BUF16820AIDAPRG4 | 功能描述:LCD Gamma緩沖器 14-Ch Vltg Generator w/2 Prog VCOM Out RoHS:否 制造商:Maxim Integrated 輸入補償電壓: 轉(zhuǎn)換速度: 電源電壓-最大:20 V 電源電壓-最小:9 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:TQFN-38 封裝:Tube |
| BUF16821 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory |
| BUF16821_1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory |
| BUF16821A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory |
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