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參數(shù)資料
| 型號： | BUF08821AIPWPR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | VIDEO CLOCK GENERATOR, PDSO20 |
| 封裝： | GREEN, PLASTIC, HTSSOP-20 |
| 文件頁數(shù)： | 26/27頁 |
| 文件大?。?/td> | 654K |
| 代理商： | BUF08821AIPWPR |
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SBOS438C – AUGUST 2008 – REVISED AUGUST 2009 ................................................................................................................................................. www.ti.com
Table 1. Quick-Reference Table of
TWO-WIRE BUS OVERVIEW
BUF08821 Addresses
The
BUF08821
communicates
over
an
BUF08821 ADDRESS:
ADDRESS
industry-standard, two-wire interface to receive data
A0 pin is LOW
in slave mode. This standard uses a two-wire,
1110100
(device acknowledges on address 74h)
open-drain interface that supports multiple devices on
A0 pin is HIGH
a single bus. Bus lines are driven to a logic LOW
1110101
(device acknowledges on address 75h)
level
only.
The
device
that
initiates
the
communication is called a master, and the devices
controlled by the master are slaves. The master
DATA RATES
generates the serial clock on the clock signal line
The two-wire bus operates in one of three speed
(SCL), controls the bus access, and generates the
modes:
START and STOP conditions.
Standard: allows a clock frequency of up to
To address a specific device, the master initiates a
100kHz;
START condition by pulling the data signal line (SDA)
Fast: allows a clock frequency of up to 400kHz;
from a HIGH to a LOW logic level while SCL is HIGH.
and
All slaves on the bus shift in the slave address byte
High-speed mode (also called Hs mode): allows a
on the rising edge of SCL, with the last bit indicating
clock frequency of up to 3.4MHz.
whether a read or write operation is intended. During
the ninth clock pulse, the slave being addressed
The BUF08821 is fully compatible with all three
responds
to
the
master
by
generating
an
modes. No special action is required to use the
Acknowledge and pulling SDA low.
device in Standard or Fast modes, but High-speed
mode must be activated. To activate High-speed
Data transfer is then initiated and eight bits of data
mode, send a special address byte of 00001 xxx, with
are sent, followed by an Acknowledge bit. During
SCL = 400kHz, following the START condition; where
data transfer, SDA must remain stable while SCL is
xxx are bits unique to the Hs-capable master, which
HIGH. Any change in SDA while SCL is HIGH is
can be any value. This byte is called the Hs master
interpreted as a START or STOP condition.
code.
provides
a
reference
for
the
Once all data have been transferred, the master
High-speed mode command code. (Note that this
generates a STOP condition, indicated by pulling
configuration
is
different
from
normal
address
SDA from LOW to HIGH while SCL is HIGH. The
bytes—the LOW bit does not indicate read/write
BUF08821 can act only as a slave device; therefore,
status.) The BUF08821 responds to the High-speed
it never drives SCL. SCL is an input only for the
command regardless of the value of these last three
BUF08821.
bits. The BUF08821 does not acknowledge this byte;
the
communication
protocol
prohibits
ADDRESSING THE BUF08821
acknowledgment of the Hs master code. Upon
receiving a master code, the BUF08821 switches on
The address of the BUF08821 is 111010x, where x is
its Hs mode filters, and communicates at up to
the state of the A0 pin. When the A0 pin is LOW, the
3.4MHz. Additional high-speed transfers may be
device acknowledges on address 74h (1110100). If
initiated without resending the Hs mode byte by
the A0 pin is HIGH, the device acknowledges on
generating a repeat START without a STOP. The
address 75h (1110101). Table 1 shows the A0 pin
BUF08821 switches out of Hs mode with the next
settings and BUF08821 address options.
STOP condition.
Other valid addresses are possible through a simple
mask change. Contact your TI representative for
information.
Table 2. Quick-Reference Table of Command Codes
COMMAND
CODE
General-Call Reset
Address byte of 00h followed by a data byte of 06h.
High-Speed Mode
00001xxx, with SCL
≤ 400kHz; where xxx are bits unique to the Hs-capable master. This
byte is called the Hs master code.
8
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): BUF08821
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| BUF08821AIPWPRG4 | 功能描述:LCD Gamma緩沖器 8 Ch LCD Gamma Buffer RoHS:否 制造商:Maxim Integrated 輸入補(bǔ)償電壓: 轉(zhuǎn)換速度: 電源電壓-最大:20 V 電源電壓-最小:9 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFN-38 封裝:Tube |
| BUF08821B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Programmable Gamma-Voltage Generator and VCOM Calibrator with Integrated Two-Bank Memory |
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| BUF08821EVM | 功能描述:放大器 IC 開發(fā)工具 BUF08821 Eval Mod RoHS:否 制造商:International Rectifier 產(chǎn)品:Demonstration Boards 類型:Power Amplifiers 工具用于評估:IR4302 工作電源電壓:13 V to 23 V |
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