
8
Standard ICs
BU9728AKV
The display data input to the command / data register (when C / D is LOW) is written to the DDRAM address and the
address consisting of the specified address + 1, which are indicated by the upper four and lower four bits of the data,
respectively. The four bits of the display data are written sequentially, starting from the MSB, to the MSB of the
DDRAM bits.
MSB
If the Rewrite DDRAM command is input (C / D is HIGH), the four bits of the display data in the Rewrite DDRAM
command are written to the specified DDRAM address.
The four bits of the display data are written sequentially, starting from the MSB, to the MSB of the DDRAM bits.
(4) Timing generator
Connecting Rf between OSC
1
 and OSC
2
 causes the internal oscillator circuit to start oscillating, and generates a dis-
play timing signal. The oscillator can also be started by inputting an external clock.
(5) LCD drive power supply
The LCD drive power supply is generated by the BU9728AKV. The LCD drive voltage (V
LCD
) is supplied by V
DD
 - V
3
,
and the power supply is generated by V
1
 = 2  V
LCD
 / 3, V
2
 = V
LCD
 / 3.
If an external bleeder resistance is used to supply the LCD drive voltage externally, the following relationship must
be observed: 
V
DD
 = V
1
 ^ 
V
2
 ^ 
V
3
 ^ 
V
SS
(6) LCD drive circuit
The LCD drive circuit is configured of four common drivers and 32 segment drivers. When oscillation begins, select-
ed waveforms are output automatically for valid common outputs by the common counter, and de-selected wave-
forms are output for other outputs.
For segment outputs, drive waveforms are output automatically by the display data and common counter.
The following page shows examples of common / segment output waveforms.
(bit3
bit0) (bit3
bit0)
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Specified address
Specified address  + 1
(bit3
bit0)
1
MSB
LSB
0
0
D3
D2
D1
D0
Rewrite DDRAM command
Display data
Fig. 3 Rf oscillator circuit
OSC
1
OSC
2
Rf
Fig. 5 Example of connection when
 using internal power supply
V
DD
V
1
V
2
V
3
V
SS
Fig. 6 Example of connection when
 using external power supply
V
DD
V
1
V
2
V
3
V
SS
Fig. 4 External clock input
OSC
1
OSC
2
OPEN
EXIT CLOCK INPUT