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參數(shù)資料
| 型號： | BU9706KS |
| 廠商： | Rohm CO.,LTD. |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | LCD segment driver |
| 中文描述： | LCD段驅(qū)動器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 59K |
| 代理商： | BU9706KS |
3
Standard ICs
BU9706KS
Pin descriptions
Pin No.
Pin name
I / O
Function
2 ~ 41
O
40
~ O
1
O
43 ~ 45
V
2
~ V
5
—
49
V
DD
—
42
V
SS
—
53
DI
1
I
54
DO
20
O
55
DI
21
I
1
DO
40
O
48
CP
I
47
LOAD
I
51
DF
I
Output pin for the liquid crystal driver. V
, V
, V
or V
is output depending on
the latch content and the DF signal. Refer to the truth table for the output level.
Power supply pin for liquid crystal drive
Logic power supply pin and liquid crystal drive power supply pin
Logic power supply pin
Data input pin for the shift register (1 to 20 bits). Data is read to the first bit of
the shift register at the clock signal falling edge.
Data output pin for the shift register (1 to 20 bits). Data is output in
synchronization with the clock signal falling edge. A 40-bit shift register is
accomplished by connecting pins 54 and 55.
Latch signal input pin for the 40-bit latch. The contents of the shift register are
transferred to O
to O
at LOAD = "H" and the data is latched at LOAD = "L". While
LOAD = "L", the latched data is held even if the contents of the shift register change.
Data output pin for the shift register (21 to 40 bits). Data is output in synchronization
with the clock signal falling edge. It is used to configure an LCD driver with more
than 40 bits by connecting it to the DI pin of the BU9706KS at the next stage.
Data input pin for the shift register (21 to 40 bits). Data is read to the 21st bit
of the shift register at the clock signal falling edge.
Clock signal input pin for the shift register. The contents of the shift register
are shifted by 1 bit only at the clock signal falling edge.
Input pin for the signal which produces AC for LCD drive.
LCD drive output pin truth table
Latch data
DF
O
n
terminal voltage
H
H
V
5
H
L
V
DD
L
H
V
3
L
L
V
2
Timing chart
Load
Load
40
1
2
3
39
40
1
2
O
1
O
40
O
39
O
38
O
2
O
1
O
40
O
39
CP
DI
1
LOAD
DF
Shifted at CP input falling.
When the LOAD input state becomes "H", the contents of the shift register are transferred to the segment
outputs O
1
to O
40
, and when it is "L", the data is latched.
Fig.1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU9716AK | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| BU9716AKV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| BU9716BK | 功能描述:LCD 驅(qū)動器 LCD DRIVER 3X32 RoHS:否 制造商:Maxim Integrated 數(shù)位數(shù)量:4.5 片段數(shù)量:30 最大時鐘頻率:19 KHz 工作電源電壓:3 V to 3.6 V 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:PDIP-40 封裝:Tube |
| BU9716BK/BKV | 制造商:ROHM 制造商全稱:Rohm 功能描述:Standard LSIs |
| BU9716BKV | 功能描述:LCD 驅(qū)動器 LCD DRIVER 3X32 RoHS:否 制造商:Maxim Integrated 數(shù)位數(shù)量:4.5 片段數(shù)量:30 最大時鐘頻率:19 KHz 工作電源電壓:3 V to 3.6 V 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:PDIP-40 封裝:Tube |
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