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參數(shù)資料
| 型號(hào)： | BU8244F |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | Cross point mixer for telephones |
| 中文描述： | 交叉點(diǎn)的電話混合器 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | BU8244F |
271
Communication ICs
BU8241F / BU8241FS / BU8242F / BU8244F
Circuit operation
Sections (1) to (3) below describe operation using the
BU8241F and BU8241FS as examples.
(1) Analog signals pass through an input amplifier and
are supplied to eight switches.
The analog input signals are turned on and off by the
switches and can thus be directed to any desired output
amplifier. Using mixing resistors connected to the out-
puts of the switches, and feedback resistors, each output
amplifier can output a signal that is a mix of up to eight
input signals.
(2) The switch states are set using a 64-bit shift register
and data latch.
The shift register reads the data at the rising edge of the
shift clock, and stores it until the next data is read at the
rising edge of the next shift clock.
After the 64 data bits have been read, supply of the rising
edge of the clock is stopped, the LATCH pin is set to
HIGH, and the switches are set. (See Figure 2 for the tim-
ing waveform.)
To change a switch setting, new setting data and shift
clocks must be supplied for 64 bits of data, and the
LATCH pin set to HIGH. If the LATCH pin is set to HIGH
before 64 shift clocks have been supplied, or after more
than 64 have been supplied, the switches cannot be set
properly. (See Table 1 for the logic of switch settings.)
Table.1 Switch Sn stage (Note 6)
(3) The power save mode is set as long as the PS pin is
kept HIGH. (See Table 2 for the power save setting logic.)
In the power save mode, the following are fixed : IN1
OUT1 (S1 = ON) and IN2 OUT2 (S10 = ON). (The oth-
er 62 switches are off.) In addition, the line current is re-
duced. When the PS pin goes from HIGH to LOW, the IC
state switches from the power save mode back to normal
operation. At that point, the state of the switch remains
in the power save mode (only S1 and S10 are on). (See
Figure 3 for the timing waveform in the power save
mode.)
(4) With the BU8242F, of the 64 data bits, the following
should be input at LOW level : D
3
, D
4
, D
11
, D
12
, D
17
to D
32
,
D
35
, D
36
, D
43
, D
44
, D
51
, D
52
, D
59
, and D
60
.
(5) With the BU8244F, DIN is 16 bits.
The ON path in the power save mode is the same for the
BU8241F and BU8241FS, but the pertinent switches are
S1 and S6.
Table.2 Power save setting theory
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