參數(shù)資料
型號: BU7331EKN-E2
廠商: Rohm Semiconductor
文件頁數(shù): 1/15頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 3CH PLL 20HQFN
標(biāo)準(zhǔn)包裝: 2,500
類型: 時鐘發(fā)生器
PLL:
輸入: 晶體
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 75MHz
除法器/乘法器: 無/無
電源電壓: 1.65 V ~ 1.95 V
工作溫度: -20°C ~ 75°C
安裝類型: 表面貼裝
封裝/外殼: 20-QFN
供應(yīng)商設(shè)備封裝: 20-HQFN
包裝: 帶卷 (TR)
1/20
www.rohm.com
2009.04 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
3ch Programmable Clock Generator
Generate
3 application clocks
BU7331EKN
●Description
The BU7331EKN integrates a 3ch PLL.The frequency of each PLL can be set via serial interface control, making it
compatible with a wide range of digital applications.
In addition, sudden frequency changes are handled via rewriting through the register, and BU7331EKN is suitable for sets
with different frequencies, resulting in more efficient parts management and shorter development time.
●Features
1) To generate clocks by connecting reference 5.0MHz ~ 48.0MHz.
2) 5.0MHz~75.0MHz output frequency range.
3) All settings and operation controlled via 2-wire serial interface
4) Individual level shifter attached to each output
5) HQFN20V package
●Application
General digital product of mobile phone, DSC, DVD-player etc.
●Absolute Maximum ratings (Ta=25℃)
Parameter
Symbol
Limits
Unit
Supply voltage (Core)
VDD_CORE
-0.2 ~ 2.2
V
Supply voltage (I/O)
VDD_IO
-0.2 ~ 4.0
V
Input Voltage
VIN
-0.2 ~ VDD+0.2
V
Storage Temperature range
Tstg
-55 ~ 125
Power dissipation
PD
599.8
*
1
mW
*
1
A measure value at mounting on 70 x 70 x 1.6mm glass epoxy substrate.
In the case of exceeding Ta=25℃, 6.0mW should be reduced per 1℃.
*
The radiation-resistance design is not carried out.
*
Operation is not guaranteed.
●Operating Conditions
Parameter
Symbol
Limits
Unit
Supply voltage (Core)
VDD_CORE
1.65 ~ 1.80 ~ 1.95
V
Supply voltage (VDD_CLK)
VDD_CLK
1.40 ~ 3.60
V
Supply voltage (VDD_SIF)
VDD_SIF
1.40 ~ 3.60 *
1
V
Input ”H” Voltage
VIH
0.8VDD ~ VDD
V
Input ”L” Voltage
VIL
0.0 ~ 0.2VDD
V
Operating Temperature
topr
-20 ~ 75
Input frequency ( xtal use ) *
2
Ref_xtal
5.0 ~ 27.0
MHz
Input frequency ( Not xtal use ) *
3
Ref_clk
5.0 ~ 48.0
MHz
5~48MHz Output Load1 (VDD_CLK=1.40~1.65V)
CL1
10 (MAX)
pF
5~48MHz Output Load 2 (VDD_CLK=1.65~3.60V)
CL2
15 (MAX)
pF
5~75MHz Output Load (VDD_CLK=2.70~3.60V)
CL3
15 (MAX)
pF
*1
When setting it as VDD_SIF=1.40V~1.45V, standby current may flow by VDD_CORE=1.90V~1.95V.
Use by VDD_CORE=1.80V is recommended.
*2
Need a resister for bias between 6PIN and 7PIN.
*3
The input amplitude level range is 0.6Vp-p ~ VDD_COREp-p.
Refer to application note about input form details.
No.09004EAT01
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