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參數(shù)資料
| 型號： | BU4S71G2-TR |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC GATE OR SINGLE 5SSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | 4S |
| 邏輯類型： | 或門 |
| 電路數(shù)： | 1 |
| 輸入數(shù)： | 2 |
| 電源電壓： | 3 V ~ 16 V |
| 電流 - 靜態(tài)（最大值）： | 1µA |
| 輸出電流高，低： | 3.4mA，3.4mA |
| 邏輯電平 - 低： | 1.5 V ~ 4 V |
| 邏輯電平 - 高： | 3.5 V ~ 11 V |
| 額定電壓和最大 CL 時的最大傳播延遲： | 30ns @ 15V，50pF |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 5-SSOP |
| 封裝/外殼： | 6-TFSOP（0.063"，1.60mm 寬），5 引線 |
| 包裝： | 帶卷 (TR) |
10
Commercial Temperature Range
IDT72V8981 3.3V Time Slot Interchange
Digital Switch 128 x 128
CS
DS
5702 drw1
5
R/
W
A5-A0
D7-D0
DTA
tCSS
tRWS
tADS
tAKD
tRDS
tSWD
tFWS
tCSH
tRWH
tADH
tAKH
tRDZ
tDHT
Figure 10. Processor Bus
Symbol
Characteristics
Min.
Typ.(2)
Max.
Unit
Test Conditions
tCSS
Chip Select Setup Time
0
ns
tRWS
Read/WriteSetupTime
5
ns
tADS
Address Setup Time
5
ns
tAKD
Acknowledgment Delay Fast
40
60
ns
C
L = 150pF
tAKD
Acknowledgment Delay Slow
4.5
cycles
C4i cycles(4)
tFWS
Fast Write Data Setup Time
10
20
ns
tSWD
Slow Write Data Delay
2.0
1.7
cycles
C4i cycles
tRDS
Read Data Setup Time
0.5
cycles
C4i cycles, C
L = 150pF
tDHT
Data Hold Time Read
20
50
75
ns
R
L = 1K
(3), C
L = 150pF
tDHT
Data Hold Time Write
10
ns
tRDZ
Read Data to High Impedance
10
50
ns
R
L = 1K
(3), C
L = 150pF
tCSH
Chip Select Hold Time
0
5
ns
tRWH
Read/Write Hold Time
0
5
ns
tADH
Address Hold Time
0
5
ns
tAKH
Acknowledgment Hold Time
20
40
ns
R
L = 1K
(3), C
L = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25
°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with R
L, with timing corrected to cancel time taken to discharge CL.
4. Processor accesses are dependent on the
C4i clock, and so some things are expressed as multiples of the C4i.
AC ELECTRICAL CHARACTERISTICS (1)
PROCESSOR BUS
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