參數(shù)資料
型號: BU3072HFV-TR
廠商: Rohm Semiconductor
文件頁數(shù): 16/22頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 1CH HVSOF6
標準包裝: 3,000
類型: 時鐘/頻率發(fā)生器
PLL:
主要目的: 數(shù)碼相機
輸入: 時鐘
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 36MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -5°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 6-SMD
供應(yīng)商設(shè)備封裝: HVSOF6
包裝: 帶卷 (TR)
Technical Note
3/21
www.rohm.com
2009.04 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
BU3071HFV,BU3072HFV,BU3073HFV,BU3076HFV,BU7322HFV,BU7325HFV
BU3073HFV(Ta=25℃, VDD=3.3V, Crystal frequency=48.0000MHz, unless otherwise specified.)
Parameter
Symbol
Limits
Unit
Conditions
Min.
Typ.
Max.
Output H voltage
VOH
2.8
-
V
IOH=-4.0mA
Output L voltage
VOL
-
0.5
V
IOL=4.0mA
Consumption current 1
IDD1
-
11
16
mA
PD=H, at no load
Consumption current 2
IDD2
-
5
mA
PD=L
Output frequency
CLK_375
-
24.3750
-
MHz
SEL=L, IN*65/16/8
CLK_545
-
24.5454
-
MHz
SEL=H, IN*45/11/8
The following parameters represent design guaranteed performance.
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1
σ
PJsSD
-
45
-
psec
※1
Long-Term-Jitter
MIN-MAX
LTJsABS
-
0.9
1.5
nsec
MIN-MAX of long-term jitter
(100 sec from trigger)
Rise time
tr
-
2.5
-
nsec
Period of transition time required for the
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Fall time
tf
-
2.5
-
nsec
Period of transition time required for the
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time
tLOCK
-
1
msec
※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 48.0000MHz, the output frequency will be as listed above.
BU3076HFV(Ta=25℃, VDD=3.3V, Crystal frequency=27.0000MHz, unless otherwise specified.)
Parameter
Symbol
Limits
Unit
Conditions
Min.
Typ.
Max.
Output H voltage
VOH
2.8
-
V
IOH=-4.0mA
Output L voltage
VOL
-
0.5
V
IOL=4.0mA
Pull-down resistance
Rpd
25
50
100
Pull-down resistance on input pin
Consumption current 1
IDD1
-
10
15
mA
54MHz output, at no load
Consumption current 2
IDD2
-
12
18
mA
67.5MHz output, at no load
Standby current
IDDst
-
1
A
OE=L
Output frequency
CLK_54
-
54.0000
-
MHz
SEL=L, IN*48/6/4
CLK_67.5
-
67.5000
-
MHz
SEL=H, IN*60/6/4
The following parameters represent design guaranteed performance.
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1
σ
PJsSD
-
50
-
psec
※1
Period-Jitter MIN-MAX
PJsABS
-
300
-
psec
※2
Rise time
tr
-
1.5
-
nsec
Period of transition time required for the
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Fall time
tf
-
1.5
-
nsec
Period of transition time required for the
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time
tLOCK
-
200
sec
※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
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