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參數(shù)資料
| 型號： | BU2661FV |
| 英文描述： | Radio Data System (RDS) Demodulator |
| 中文描述： | 廣播數(shù)據(jù)系統(tǒng)（RDS）解調(diào)器 |
| 文件頁數(shù)： | 6/6頁 |
| 文件大小： | 83K |
| 代理商： | BU2661FV |
External dimensions (Units: mm)
919
Audio ICs
BU2661FV
Circuit operation
Output data timing
The clock (RCLK) frequency is 1187.5Hz. Depending on the state of the internal PLL clock, the data (RDATA) is replaced
in synchronous with either the rising or falling edge of the clock. To read the data, you may choose either the rising or
falling edge of the clock as the reference. The data is valid for 416.7
μ
s. after the reference clock edge.
QUAL pin operation: Indicates the quality of the demodulated data.
(1)
Good data: HI
(2)
Poor data: LO
(3)
No signal: LO
(4)
Noise input: HI / LO (flutters)
ARI pin operation: ARI / RDS distinction
(1)
ARI: HI
(2)
RDS
ARI: HI
(3)
RDS: LO
(4)
No signal: unstable
(5)
Noise input: unstable
RESET input pin: Resets the digital circuit. Connect to ground or leave open during operation.
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