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參數(shù)資料
| 型號： | BU2365FV-E2 |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN W/VCXO SSOP-B24 |
| 標準包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器，VCXO |
| PLL： | 是 |
| 主要目的： | 用于 DVD 播放器的音頻視頻設(shè)備 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:5 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 54MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -10°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.220"，5.60mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SSOPB |
| 包裝： | 帶卷 (TR) |
DS650F1
9
CS4461
4.3
Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies and clocks
are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the min-
imum specified operating voltages to prevent power glitch related issues.
The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de-
lay between the release of reset and the generation of valid output, due to the finite output impedance of
FILT+ and the presence of the external capacitance.
4.4
Overflow Detection
The CS4461 includes modulator overflow detection, indicated on pin 15, OVERFLOW (open drain, active
low). OVERFLOW will go to a logical low as soon as an overrange condition is detected. The data will re-
main low until the condition is cleared.
4.5
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4461 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 1 shows the recommended power ar-
rangements, with VA and VDP connected to clean supplies. VDP, which powers the digital logic, may be
run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no
additional devices should be powered from VDP. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulator. The FILT+
and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path
from FILT+ to GND. The CDB44800 evaluation board demonstrates the optimum layout and power supply
arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
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