參數(shù)資料
型號(hào)： BU2280FV-E2
廠商： Rohm Semiconductor
文件頁(yè)數(shù)： 21/26頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN DVD-VIDEO SSOP-B24
標(biāo)準(zhǔn)包裝： 2,000
類(lèi)型： 時(shí)鐘/頻率發(fā)生器，VCXO
PLL： 是
主要目的： 用于 DVD 播放器的音頻視頻設(shè)備
輸入： 晶體
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:8
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 36.87MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -5°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-TSSOP（0.220"，5.60mm 寬）
供應(yīng)商設(shè)備封裝： 24-SSOPB
包裝： 帶卷 (TR)
BU2280FV, BU2360FV, BU2362FV
Technical Note
4/23
www.rohm.com
2012.02 - Rev.B
2012 ROHM Co., Ltd. All rights reserved.
0
Input Voltage [V]
Out
put
V
ol
tage
[V
]
VthLVthH
Vhys
0.2VDD
0.8VDD
◎BU2362FV(VDD=3.3V, Ta=25℃, Crystal frequency 27.0000MHz, unless otherwise specified.)
Parameter
Symbol
Limits
Unit
Conditions
Min.
Typ.
Max.
Output L voltage
VOH
2.4
-
V
IOH=-4.0mA
Output H voltage
VOL
-
0.4
V
IOL=4.0mA
Action circuit current
IDD
-
35
45
mA
At no load
CLK512FS
CLK512-44
-
22.5792
-
MHz
At FSEL1=OPEN XTAL*3136/625/6
CLK512-48
-
24.5760
-
MHz
At FSEL1=L XTAL*2048/375/6
CLKA
CLKA-A
-
16.9344
-
MHz
At FSEL1=OPEN XTAL*3136/625/8
CLKA-B
-
36.8640
-
MHz
At FSEL1=L XTAL*2048/375/8
CLK36M
-
36.8640
-
MHz
XTAL*2048/375/4
CLK33M
-
33.8688
-
MHz
XTAL*3136/625/4
CLK16M
-
16.9344
-
MHz
XTAL*3136/625/8
CLK27M
-
27.0000
-
MHz
XTAL direct out
Duty
45
50
55
%
Measured at a voltage of 1/2 of VDD
Period-Jitter 1
σ
P-J 1
σ
-
70
-
psec
*1
Period-Jitter MIN-MAX
P-J
MIN-MAX
-
420
-
psec
*2
Rise Time
Tr
-
2.5
-
nsec
Period of transition time required for the
output reach 80% from 20% of VDD.
Fall Time
Tf
-
2.5
-
nsec
Period of transition time required for the
output reach 20% from 80% of VDD.
Output Lock-Time
Tlock
-
1
msec
*3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
Common to BU2280FV, BU2360FV and BU2362FV:
*1
Period-Jitter
1
σ
This parameter represents standard deviation (
1 ) on cycle distribution data at the time when the output clock cycles
are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
*2
Period-Jitter
MIN-MAX
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock
cycles are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
*3
Output Lock-Time
The Lock-Time represents elapsed time after power supply turns ON to reach a 3.0V voltage, after the system is
switched from Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized
at a specified frequency, respectively.
BU2360FV
4 This parameter represents lower and upper limit voltages at the Schmitt trigger input PIN having hysteresis
characteristics shown in figure below. The width requested by these differences is assumed to be a hysteresis width.
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