參數(shù)資料
型號(hào): BU2092FV-E2
廠商: Rohm Semiconductor
文件頁數(shù): 15/18頁
文件大?。?/td> 0K
描述: IC DRVR SER/PAR I/O 12B SSOP-B20
標(biāo)準(zhǔn)包裝: 1
類型: 驅(qū)動(dòng)器
驅(qū)動(dòng)器/接收器數(shù): 12/0
電源電壓: 2.7 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 20-LSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP-B
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1376 (CN2011-ZH PDF)
其它名稱: BU2092FV-E2DKR
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
6/24
www.rohm.com
2009.06 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
●Operating description
(1) Data clear
When the reset terminal (CLR, CLB) is set to “L”, the content of all latch circuits are set to “H”, and all parallel outputs are
initialised.
(For model with reset terminal only)
(2) Data transfer
Serial data is sequentially input to the shift register during the rise of the clock time (strobe signal is not active). When
the strobe signal is active, the content of the shift register are transferred to the latch circuit.
(3) Cascade connection
Serial input data is output from the serial output through the shift register, regardless of the strobe signal.
(except
for
BU2050F,
BU2092F/BU2092FV)
●Application circuit
Fig. 1
●Interfaces
BU2050F
BU2092F/BU2092FV
DATA, CLOCK, STB, CLR
P1~P8
DATA, CLOCK, LCK, OE
Q0~Q11
BU2099FV
BU2152FS
DATA, CLOCK, LCK, OE
Q0~Q11
SO
CLOCK, DATA, STB, CLB
BU2152FS
P1~P28
SO
VDD
Serial data input
Clock input
Strobe input
Latch input
P1 P2
Pn-2 Pn-1 Pn
Serial data output
VSS
P1 P2
Pn-2 Pn-1 Pn
VSS
VDD
VSS
MPU
C1
(*)
(*C1 must be placed as close to the terminal as possible.)
VDD
Serial data input
Clock input
Strobe input
Latch input
Serial data output
INPUT
GND(VSS)
VDD
GND(VSS)
VDD
OUTPUT
GND(VSS)
IN
GND(VSS)
VDD
OUT
GND(VSS)
VDD
OUT
GND(VSS)
VSS
VDD
VSS
GND(VSS)
VDD
GND(VSS) GND(VSS)
GND(VSS)
VDD
GND(VSS)
VDD
GND(VSS)
VDD
GND(VSS)
VDD
GND(VSS)
VDD
IN
(only OE pin)
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