參數(shù)資料
型號(hào)： BU1924F
廠(chǎng)商： Rohm CO.,LTD.
英文描述： RDS / RBDS decoder
中文描述： 鐵路發(fā)展策略/無(wú)線(xiàn)廣播數(shù)據(jù)解碼器
文件頁(yè)數(shù)： 4/5頁(yè)
文件大?。?/td> 81K
代理商： BU1924F
BU1924 / BU1924F
Audio ICs
!
Electrical characteristics
(unless otherwise noted, Ta = 25
°
C, V
DD1
= V
DD2
= 5.0V, V
SS1
= V
SS2
= 0.0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
Operating current
I
DD
4.5
7.0
mA
I
DD1
+
I
DD2
Reference voltage
Vref
1/2V
DD1
V
Pin 3
Input current 1
I
IN1
1.0
μ
A
MUX
MUX
Output current 1
I
OUT1
1.0
μ
A
V
IN
=
V
DD1
V
IN
=
V
DD1
Input current 2
I
IN2
1.0
μ
A
XI
XI
Output current 2
I
OUT2
1.0
μ
A
V
IN
=
V
DD2
V
IN
=
V
DD2
Output high level voltage 1
V
OH1
V
DD2
1.0
V
DD2
0.3
V
RCLK RDATA QUAL I
O
=
1.0mA
Output low level voltage 1
V
OL1
0.2
1.0
V
RCLK RDATA QUAL I
O
=
1.0mA
RDS detector sensitivity
SRDS
0.5
1.0
mVrms
RDS input level
MRDS
1.0
300
mVrms
ARI detector sensitivity
SARI
1.5
3.0
mVrms
Data rate
DRATE
1187.5
Hz
Clock transient vs. data
CT
4.3
μ
s
Center frequency
FC
56.5
57.0
57.5
kHz
Gain
GA
20
23
26
dB
F
=
57.0kHz
Attenuation 1
ATT1
18
22
dB
57kHz
±
4kHz
Attenuation 2
ATT2
65
80
dB
38kHz
Attenuation 3
ATT3
35
50
dB
67kHz
S / N ratio
SN
30
40
dB
57kHz V
IN
=
3mVrms
Maximum input level
VMAX1
500
mVrms
Demodulator
Not designed for radiation resistance.
Filter block
!
Output data timing
T
1
T
5
T
1
=T
2
=4.3
μ
S
RCLK
RDATA
T
3
=T
4
=421
μ
S
T
5
=T
6
=416.7
μ
S
T
1
T
3
T
4
T
2
T
6
T
2
The clock (RCLK) frequency is 1187.5Hz. Depending on the state of the internal PLL clock, the data (RDATA) is replaced
in synchronous with either the rising or falling or falling edge of the clock. To read the data, you may choose either the
rising or falling edge of the clock as the reference. The data is valid for 416.7
μ
s. after the reference clock edge.
QUAL pin operation : Indicates the quality of the demodulated data.
(1) Good data : HI
(2) Poor data : LO
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