參數(shù)資料
型號： BU-69200
英文描述： MIL-STD-1553 Components |ACE-Core
中文描述： 符合MIL - STD - 1553器件|進洞核心
文件頁數(shù)： 2/4頁
文件大?。?/td> 373K
代理商： BU-69200
Data Device Corporation
www.ddc-web.com
BU-69200
REV CODE 1
BC Architecture
- Highly Autonomous Message Sequence Control
- Defined Set of 20 Instructions
- Control/Status Blocks for Individual Messages
- Minor and Major Frame Scheduling
- Asynchronous Message Insertion
- Conditional Branching and Subroutines
- General Purpose Queue: Message Status, Time,
Immediate and Indirect Data
- Fully User-definable Interrupts
- Legacy Mode for Compatibility with ACE and
Mini-ACE Applications
RT Architecture
- Supports MIL-STD-1553A/B Notice 2, STANAG-3838 RT,
and MIL-STD-1760 Stores Management
- Choice of Subaddress Single Message, Double
Buffering, or Circular Buffering; or Global Circular
Buffering
- 32-Entry Interrupt Status Queue
- 50% and 100% Circular Buffer Rollover Interrupts
- Stack with Descriptors for Individual Messages
- Message Status, Time Tag, Command Word,
Data Pointer
- Programmable Command Illegalization
- Programmable Busy by Subaddress
- Interrupts on All Messages, or Individual Subaddresses
and/or Mode Codes
- Hardwired or Software-Programmable RT Address
- Available with Option for RT AUTO-BOOT with BUSY
Bit Set for MIL-STD-1760 Applications
- Compatible with ACE and Mini-ACE Applications
Monitor Architecture
- Selective Message Monitor
- Filter Based on RT Address, T/R* bit, Subaddress
- True Message Monitor
- Command Stack
- Message Status, Time Tag, Command Word,
Data Pointer
- Data Stack
- All Monitored Words Following (first) Command Word
- 50% and 100% Rollover Interrupts for Command
and Data Stacks
- 32-Entry Interrupt Status Queue
- Simultaneous RT/Message Monitor Option
Specifications
PARAMETER
MIN
TYP
MAX UNITS
ASIC GATE COUNT
20,000
CORE CONFIGURATIONS
BC/RT/Monitor, RT-only
PROTOCOLS SUPORTED
MIL-STD-1553A/B Notice 2
STANAG-3838
MIL-STD-1760
MEMORY SUPPORT
1553 Message,
Control, and Status RAM
Protocol Self-Test ROM or RAM
64K X 16 or 64K X 17
4K X 24
CLOCK INPUT
Number Of Clock Domains
Frequency: Nominal Values
Default Mode
Option
Option
Option
1
16.0
12.0
10.0
20.0
MHz
MHz
MHz
MHz
PARAMETER
MIN
TYP
MAX UNITS
1553 MESSAGE TIMING
BC Intermessage Gap
- Non-enhanced
(Mini-ACE compatible)
BC mode
- Enhanced BC Mode
9.5
μS
10.0 to
10.5
μS
BC/RT/MT Response Timeout
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
RT Response Time
(mid-parity to mid-sync)
Transmitter Watchdog Timeout
17.5
21.5
49.5
127
18.5
22.5
50.5
129.5
91.5
23.5
51.5
131
μS
μS
μS
μS
4
7
μS
μS
660.5
SOURCE CODE LANGUAGE
VHDL
SUPPORT DOCUMENTATION
ACECore IP User's Guide
Enhanced Mini-ACE User's
Guide
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