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參數資料
| 型號： | BU-65145F2-310W |
| 元件分類： | 串行ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| 中文描述： | 控制器雜項-數據表參考 |
| 文件頁數： | 5/24頁 |
| 文件大?。?/td> | 219K |
| 代理商： | BU-65145F2-310W |
13
DATA 1514131211 10 9 8 7 6 54 32 10 P DATA 15 1413 12 1110 9 87 6 5 43 21 0 P
STATUS151413121110 9 8 7 6 54 32 10 P
4-12s RECEIVING AT RESPONSE TIME
4.7±.3s
1.1±.2s
225-275ns
475-550ns
DTGRT
IS RECOGNIZED
DATA TRANSFER
STARTS, SUBSYSTEM
SHOULD BE DRIVING
THE DATA BUS
INTERNAL DATA
SUFFERS ARE NOW
INPUTS
1st DATA WORD
TRANSFER
SUBSYSTEM DATA
MUST BE VALID
ENCODER REGISTERS
AVAILABLE FOR NEXT
WORD RTU
REQUESTS DATA BUS
FOR 2nd DATA WORD
TRANSFER
INTERNAL DATA
BUFFERS ARE NOW
INPUTS
2nd DATA WORD
TRANSFER
SUBSYSTEM DATA
MUST BE VALID
50ns min
DTGRT
IS RECOGNIZED
DATA TRANSFER
STARTS, SUBSYSTEM
SHOULD BE DRIVING
THE DATA BUS
225-275ns
475-550ns
100ns max
note 6
CURRENT WORD COUNT=00001
100-150ns
300ns max
s max
9.35s max
300ns max
100-150ns
CURRENT WORD COUNT=00010
100ns max
note 6
2. EACH WORD IS DRIVEN FOR
18-19S ON D15-D0.
IF BUF ENA IS ACTIVE THE LAST WORD IS AVAILABLE FOR 3.5-4S SINCE THE STATUS WORD MUST BE SUPPORTED.
3. DATA BUS IS SHOWN WITH BUF ENA CONNECTED TO DTACK (SEE PIN FUNCTION TABLE, PIN 67)
4. THE MAXIMUM RESPONSE TIME FROM DTREQ TO DTGRT TO GUARANTEE A SUCCESSFUL TRANSFER IS 2.1S FROM THE COMMAND WORD
AND 9.35S FROM THE DATA TRANSFER FROM THE SUBSYSTEM. THE POSITION OF DTACK WILL VARY DEPENDING ON WHEN DGRT IS ISSUED.
THE TIME WILL BE 100Ns MIN TO 150nS FROM DTREQ.
5. RTFAIL IS CLEARED WHEN THE STATUS WORD IS TRANSMITTED. ONCE SET, FLAG WILL REMAIN SET FOR THE ENTIRE MESSAGE.
THE INCMD FALLING EDGE CAN BE USED TO LATCH RTFAIL STATUS.
6. 100nS MIN REPRESENTS SETUP TIME FOR VALID DATA BEFORE DTSTR GOES LOW FOR A WRITE CYCLE.
A READ CYCLE REQUIRES VALID DATA 150nS MAX AFTER DTACK GOES LOW.
1. LEGEND
DON'T CARE
DATA BUS UNDEFINED
REPRESENTS THE SEQUENCE OF EVENTS IF THE COMMAND WAS BROADCAST.
NOTE: NO STATUS WOULD BE TRANSMITTED ON1553 BUS.
NOTES
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