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參數(shù)資料
| 型號(hào)： | BU-65144F2-190W |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 11/24頁(yè) |
| 文件大?。?/td> | 219K |
| 代理商： | BU-65144F2-190W |
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19
Remote Terminal Flag--Input signal used
to control the terminal flag bit in the sta-
tus register. If LOW when the status
word is updated, the terminal flag bit
would be set; if HIGH, it would be
cleared. Normally connected to RTFAIL .
Multiplexed address line output. When
INCMD is LOW or A5 thru A9 are all
zeroes or all ones (Mode Command), it
represents the latched output of the 3rd
MSB in the word count field of the com-
mand word. When INCMD is HIGH and
A5 thru A9 are not all zeroes or all ones,
it represents the 3rd MSB of the current
word counter.
Input from the LOW side of the primary
side of the coupling transformer that con-
nects to the B channel of the 1553 Bus.
+5 V input power supply connection for
the B channel transceiver.
-15V/-12V input power supply connection
for the B channel transceiver (Note 5).
HIGH, output to the primary side of the
coupling transformer that connects to the
B channel transceiver.
Input of Address Parity Bit. The combina-
tion of assigned terminal address and
ADDRP must be odd parity for the RT to
work.
Input of the 2nd LSB of the assigned ter-
minal address.
Input of the 2nd MSB of the assigned ter-
minal address.
Power supply return for RTU digital logic
section.
+5V input power supply connection for
RTU digital logic section.
A0
(WCO/
CSWO)
A2
(WC2/
CSW2)
RXDATA B
+5VB
-VB
TXDATA B
ADDRP
ADDRB
ADDRD
GND
+5V
78
80
39
37
35
33
31
29
27
25
23
Bi-directional parallel data bus Bit 14
DB14
21
Bi-directional parallel data bus Bit 12
DB12
19
Bi-directional parallel data bus Bit 10
DB10
17
Bi-directional parallel data bus Bit 8
DB8
15
Bi-directional parallel data bus Bit 6
DB6
13
Bi-directional parallel data bus Bit 4
DB4
11
Bi-directional parallel data bus Bit 2
DB2
9
Bi-directional parallel data bus Bit 0 (LSB)
DB0
7
Latched output of the 2nd LSB in the sub-
address field of the command word.
A6
(SA1)
5
Latched output of the 2nd MSB in the
subaddress field of the command word.
A8
(SA3)
3
New Bus Grant -- LOW level output pulse
(166ns) used to indicate the start of a
new protocol sequence in response to the
command word just received.
NBGT
43
HIGH output to the primary side of the
coupling transformer that connects to the
A channel of the 1553 Bus.
TXDATA A
45
-15V/-12V input power supply connection
for the A Channel transceiver (Note 5).
+5V input power supply connection for
the A channel transceiver.
-VA
+5VA
47
49
75
77
38
36
34
32
30
28
26
24
22
61
60
59
58
—
56
55
54
53
52
51
20
50
18
49
16
48
14
47
12
46
10
45
8
44
6
43
4
42
2
41
40
42
39
38
—
44
46
FUNCTION
78-
Pin
Flat-
Pack
DESCRIPTION
PACKAGE & PIN
82-
Pin
Flat-
Pack
PIN FUNCTION TABLE (continued)
SSFLAG
56
SSBUSY
58
Watchdog Timeout test point--DO NOT
USE. (See note 3)* (input).
TEST 1
60
RTFLAG
62
Input resets entire RT when LOW.
RESET
64
Buffer Enable-- input used to enable or
tri-state the internal data bus buffers
when they are driving the bus. When
LOW, the data bus buffers are enabled.
Could be connected to DTACK, if RT is
sharing the same data bus as the
subsystem. (see note 2)*.
BUF ENA
66
16MHz Clock Input--input for the master
clock used to run RTU circuits.
16MHz IN
68
GBR
70
RD/WR
72
Data Transfer Acknowledge-- active LOW
output signal during data transfers to or
from the subsystem indicating the RTU
has received the DTGRT in response to
DTREQ and is presently doing the trans-
fer. Can be connected directly to
(BUF ENA) for control of tri-state data
buffers; and to tri-state address buffer
control lines, if they are used.
DTACK
76
53
72
55
71
A4
(WC4/
CWC4)
74
57
70
63
71
59
69
61
68
63
67
65
66
67
65
69
64
62
73
FUNCTION
78-
Pin
Flat-
Pack
DESCRIPTION
PACKAGE & PIN
82-
Pin
Flat-
Pack
PIN FUNCTION TABLE (continued)
78-
Pin
QIP
78-
Pin
QIP
Read/Write-- output signal that controls
the direction of the internal data bus
buffers. Normally, the signal is LOW and
the buffers drive the data bus. When
data is needed from the subsystem, it
goes HIGH to turn the buffers around and
the RT now appears as an input. The
signal is HIGH only when DTREQ is
active (LOW).
Subsystem Busy-- input from the subsys-
tem used to control the busy bit in the
status register. If LOW when the status
word is updated, the busy bit will be set,
if HIGH it will be cleared. If the busy bit
is set in the status register, no data will
be requested from the subsystem in
response to a transmit command. On
receive commands, data will be trans-
ferred to the subsystem.
Subsystem Flag-- input from the subsys-
tem used to control the subsystem flag
bit in the status register. If LOW when
the status word is updated, the subsys-
tem flag will be set; if HIGH it will be
cleared.
Multiplexed address line output. When
INCMD is LOW or A5 thru A9 are all
zeroes or all ones (Mode Command), it
represents the latched output of the MSB
in the word count field of the command
word. When INCMD is HIGH and A5 thru
A9 are not all zeroes or all ones, it repre-
sents the MSB of the current word
counter.
Good Block Received--LOW level output
pulse (.5s) used to flag the subsystem
that a valid, legal, non-mode receive
command with the correct number of
data words has been received without a
message error and successfully trans-
ferred to the subsystem.
Multiplexed address line output. When
INCMD is LOW or A5 thru A9 are all
zeroes or all ones (Mode Command), it
represents the latched output of the LSB
in the word count field of the command
word. When INCMD is HIGH and A5 thru
A9 are not all zeroes or all ones, it repre-
sents the LSB of the current word counter.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-65144F2-190Y | Controller Miscellaneous - Datasheet Reference |
| BU-65144F2-190Z | Controller Miscellaneous - Datasheet Reference |
| BU-65145-130Y | Controller Miscellaneous - Datasheet Reference |
| BU-65145-130Z | Controller Miscellaneous - Datasheet Reference |
| BU-65145-140 | Controller Miscellaneous - Datasheet Reference |
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