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參數(shù)資料
| 型號： | BU-62864G4-490Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 79/99頁 |
| 文件大?。?/td> | 578K |
| 代理商： | BU-62864G4-490Q |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
80
Figure 16 illustrates the process of reading an ACE memory (BAR0) or ACE
register (BAR1 00-FCh) location. The actual read shown is that of a single word
read, due to the ~600 nS response time shown, see following text and timing
formula tables. If the write FIFO is empty and there isn’t a previous Delayed Read
Request (DRR) pending, a read from these locations enques a DRR, which is then
processed by the PACE. If either of these conditions is true, the PACE will respond
with a Retry, but will not enque any new DRR.
The PACE responds to the first read with a Retry. By PCI rules the master must
repeat the same exact request until it completes. This is shown by the master’s
second read attempt, which also produces a Retry. Each repeated read request
from the master will be target terminated with a Retry until the data from the
enqued DRR is present in the PACE’s PCI interface. The successful completion is
shown at the third read request, which produces a Disconnect with Data.
This process applies to any memory read from legal address space OTHER than
the PCI-ACE interface registers at BAR1 offset 800-81Ch.
Note that one of the conditions for enquing a DRR is that the write FIFO must be
empty. For efficient use of PCI bus bandwidth, the driver software should be
written such that it checks the FIFO condition (BAR1 800-81CH registers are
directly readable, bypassing the DRR mechanism) before reading from the other
PACE locations. If the FIFO is not empty (BAR1 800h bit 30 is the FIFO not
empty flag) and a read is attempted, the bus master will be using PCI bandwidth
repeating the read request while the FIFO empties, BEFORE the read request is
actually enqued as a DRR.
When reading ACE memory (BAR0), any combination of byte enables is
supported, but the PACE will drive the entire word onto the AD lines when only a
single byte enable in the word is asserted.
When reading ACE registers (BAR 00-FCh), byte enable combinations where
only a single byte within a word is requested will cause the PACE to terminate
the transaction with a target abort. The PACE will drive all zeros onto the AD
lines if only the upper word byte enables or no byte enables are asserted.
With relation to actual timing, PCI double word reads of ACE memory (BAR0) will
take longer to complete than single word ACE memory reads because the
internal ACE memory data path is 16 bits wide. In addition, read cycles will take
longer to complete with slower ACE clocks. See Table 63 for min/max formulas
for calculating completion time for the various types of reads.
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