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參數(shù)資料
| 型號： | BU-62864B3-120Y |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| 封裝： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128 |
| 文件頁數(shù)： | 68/93頁 |
| 文件大?。?/td> | 504K |
| 代理商： | BU-62864B3-120Y |
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Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
70
load the Time Tag Register with a specified value; and an instruction enabling
the BC Message Sequence Control engine to write the value of the Time Tag
Register to the General Purpose Queue.
INTERRUPTS
The PCI Enhanced Mini-ACE series terminals provide many programmable
options for interrupt generation and handling. The interrupt output pin (INT*) has
three software programmable mode of operation: a pulse , a level output cleared
under software control, or a level output automatically cleared following a read of
the Interrupt Status Register (#1 or #2).
Individual interrupts are enabled by the two Interrupt Mask Registers. The host
processor may determine the cause of the interrupt by reading the two Interrupt
Status Registers, which provide the current state of interrupt events and
conditions. The Interrupt Status Registers may be updated in two ways. In one
interrupt handling mode, a particular bit in Interrupt Status Register #1 or #2 will
be updated only if the event occurs and the corresponding bit in Interrupt Mask
Register #1 or #2 is enabled.
In the enhanced interrupt handling mode, a
particular bit in the one of the Interrupt Status Registers will be updated if the
event/condition occurs regardless of the value of the corresponding Interrupt
Mask Register bit. In either case, the respective Interrupt Mask Register (#1 or
#2) bit is used to enable an interrupt for a particular event/condition.
The PCI Enhanced Mini-ACE supports all the interrupt events from ACE/Mini-
ACE (Plus) and Enhanced Mini-ACE including RAM Parity Error, Transmitter
Timeout, BC/RT Command Stack Rollover, MT Command Stack and Data Stack
Rollover, Handshake Error, BC Retry, RT Address Parity Error, Time Tag
Rollover, RT Circular Buffer Rollover, BC Message, RT Subaddress, BC End-of-
Frame, Format Error, BC Status Set, RT Mode Code, MT Trigger, and End-of-
Message.
For the PCI Enhanced Mini-ACE’s Enhanced BC mode, there are four user-
defined interrupt bits. The BC Message Sequence Control Engine includes an
instruction enabling it to issue these interrupts at any time.
For RT and Monitor modes, the PCI Enhanced Mini-ACE architecture include an
Interrupt Status Queue. This provides a mechanism for logging messages that
result in interrupt requests. Entries to the Interrupt Status Queue may be filtered
such that only valid and/or invalid messages will result in entries on the queue.
The PCI Enhanced Mini-ACE incorporates additional interrupt conditions beyond
ACE/Mini-ACE (Plus), based on the addition of Interrupt Mask Register #2 and
Interrupt Status Register #2. This is accomplished by chaining the two Interrupt
Status Registers using the INTERRUPT CHAIN BIT (bit 0) in Interrupt Status
Register #2 to indicate that an interrupt has occurred in Interrupt Status Register
#1.
Additional interrupts include “Self-Test Completed”, masking bits for the
Enhanced BC Control Interrupts, 50% Rollover interrupts for RT Command
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-62864B3-140K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| BU-62864B3-150Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| BU-62864B3-182 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| BU-62864B4-130K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| BU-62864B4-140 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
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