參數(shù)資料
型號(hào)： BU-62864B3-112Q
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
封裝： 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128
文件頁(yè)數(shù)： 73/93頁(yè)
文件大?。?/td> 504K
代理商： BU-62864B3-112Q
Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
75
.
Table 59. CPU Writing Ram or Registers (Shown for 16-Bit, Buffered, Nonzero Wait Mode)
3.3V LOGIC
UNIT
REF
DESCRIPTION
MIN TYP MAX
t1
SELECT* and STRBD* low setup time prior to clock rising edge
(Note 2,10)
15
ns
t2
SELECT* and STRBD* low to IOEN* low (uncontended access @
20 MHz) (Notes 2,6)
105
ns
(contended access, with ENHANCED CPU ACCESS
= “0”, @20 MHz) (Notes 2,6)
2.2
s
(contended access, with ENHANCED CPU ACCESS
= “1”, @20 MHz) (Notes 2,6)
355
ns
(uncontended access @16 MHz) (Notes 2,6)
117
ns
(contended access, with ENHANCED CPU ACCESS
= “0”, @16 MHz) (Notes 2,6)
2.8
s
(contended access, with ENHANCED CPU ACCESS
= “1”, @16 MHz) (Notes 2,6)
430
ns
(uncontended @12 MHz) (Notes 2,6)
138
ns
(contended access, with ENHANCED CPU ACCESS
= “0”, @12 MHz) (Notes 2,6)
3.7
s
(contended access, with ENHANCED CPU ACCESS
= “1”, @12 MHz) (Notes 2,6)
555
ns
(uncontended access @10 MHz) (Notes 2,6)
155
ns
(contended access, with ENHANCED CPU ACCESS
= “0”, @10 MHz) (Notes 2,6)
4.4
s
(contended access, with ENHANCED CPU ACCESS
= “1”, @10 MHz) (Notes 2,6)
655
ns
t3
Time for MEM/REG* and RD/WR* to become valid following
SELECT* and STRBD* low (@20 MHz) (Notes 3,4,5,7)
10
ns
@16 MHz (Notes 3,4,5,7)
16
ns
@12 MHz (Notes 3,4,5,7)
27
ns
@10 MHz (Notes 3,4,5,7)
35
ns
T4
Time for address to become valid following SELECT* and STRBD*
low (@20 MHz).
12
ns
@16 MHz
25
ns
@12 MHz
45
ns
@10 MHz
62
ns
Time for data to become valid following SELECT* and STRBD* low
(at 20 MHz)
32
ns
at 16 MHz
45
ns
at 12 MHz
65
ns
t5
at 10 MHz
82
ns
t6
CLOCK IN rising edge delay to IOEN* falling edge (Note 6)
40
ns
t7
SELECT* hold time following IOEN* falling (Note 2)
0
ns
t8
MEM/REG*, RD/WR* setup time prior to CLOCK IN falling edge
(Notes 3,4,5,7)
15
ns
t9
MEM/REG*, RD/WR* hold time following CLOCK IN falling edge
(Notes 3,4,5,7)
35
ns
t10
Address valid setup time prior to CLOCK IN rising edge (Notes 7,8,)
35
ns
t11
Data valid setup time prior to CLOCK IN rising edge
15
ns
t12
Address valid hold time following CLOCK IN rising edge (Notes 7, 8,
30
ns
相關(guān)PDF資料
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BU-62864B3-120Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
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