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    參數(shù)資料
    型號(hào)： BU-62843G3-100
    廠商： DATA DEVICE CORP
    元件分類： 微控制器/微處理器
    英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    封裝： 1 INCH, CERAMIC, QFP-72
    文件頁數(shù)： 71/99頁
    文件大小： 578K
    代理商： BU-62843G3-100
    Data Device Corporation
    62743_pre7_noSA-DB.DOC
    www.ddc-web.com
    8-07-02
    73
    Individual interrupts are enabled by the two Interrupt Mask Registers. The host
    processor may determine the cause of the interrupt by reading the two Interrupt
    Status Registers, which provide the current state of interrupt events and
    conditions. The Interrupt Status Registers may be updated in two ways. In one
    interrupt handling mode, a particular bit in Interrupt Status Register #1 or #2 will
    be updated only if the event occurs and the corresponding bit in Interrupt Mask
    Register #1 or #2 is enabled.
    In the enhanced interrupt handling mode, a
    particular bit in the one of the Interrupt Status Registers will be updated if the
    event/condition occurs regardless of the value of the corresponding Interrupt
    Mask Register bit. In either case, the respective Interrupt Mask Register (#1 or
    #2) bit is used to enable an interrupt for a particular event/condition.
    The PCI Enhanced Mini-ACE supports all the interrupt events from ACE/Mini-
    ACE (Plus) and Enhanced Mini-ACE including RAM Parity Error, Transmitter
    Timeout, BC/RT Command Stack Rollover, MT Command Stack and Data Stack
    Rollover, Handshake Error, BC Retry, RT Address Parity Error, Time Tag
    Rollover, RT Circular Buffer Rollover, BC Message, RT Subaddress, BC End-of-
    Frame, Format Error, BC Status Set, RT Mode Code, MT Trigger, and End-of-
    Message.
    For the PCI Enhanced Mini-ACE’s Enhanced BC mode, there are four user-
    defined interrupt bits. The BC Message Sequence Control Engine includes an
    instruction enabling it to issue these interrupts at any time.
    For RT and Monitor modes, the PCI Enhanced Mini-ACE architecture include an
    Interrupt Status Queue. This provides a mechanism for logging messages that
    result in interrupt requests. Entries to the Interrupt Status Queue may be filtered
    such that only valid and/or invalid messages will result in entries on the queue.
    The PCI Enhanced Mini-ACE incorporates additional interrupt conditions beyond
    ACE/Mini-ACE (Plus), based on the addition of Interrupt Mask Register #2 and
    Interrupt Status Register #2. This is accomplished by chaining the two Interrupt
    Status Registers using the INTERRUPT CHAIN BIT (bit 0) in Interrupt Status
    Register #2 to indicate that an interrupt has occurred in Interrupt Status Register
    #1.
    Additional interrupts include “Self-Test Completed”, masking bits for the
    Enhanced BC Control Interrupts, 50% Rollover interrupts for RT Command
    Stack, RT Circular Buffers, MT Command Stack, and MT Data Stack; BC Op
    Code Parity Error, (RT) Illegal Command, (BC) General Purpose Queue or
    (RT/MT) Interrupt Status Queue Rollover, Call Stack Pointer Register Error, BC
    Trap Op Code, and four User-Defined interrupts for the Enhanced BC mode.
    RAM PARITY
    The BC/RT/MT version of the PCI Enhanced Mini-ACE is available with options of
    4K or 64K words of internal RAM. For the 64K option, the RAM is 17 bits wide. The
    64K X 17 internal RAM allows for parity generation for RAM write accesses, and
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