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參數(shù)資料
| 型號(hào)： | BU-61865G3-740K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 25.40 X 25.40 MM, 3.94 MM HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 45/60頁 |
| 文件大?。?/td> | 700K |
| 代理商： | BU-61865G3-740K |
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5
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
Rev. C
INTRODUCTION
The BU-61740/61743/61745 RT, and BU-61840/61843/61845/
61860/61864/61865 BC/RT/MT Enhanced Mini-ACE family of
MIL-STD-1553 terminals comprise a complete integrated inter-
face between a host processor and a MIL-STD-1553 bus. All
members of the Enhanced Mini-ACE family are packaged in the
same 1.0 square inch flatpack package. The Enhanced Mini-
ACE hybrids are nearly 100% footprint and software compatible
with the previous generation Mini-ACE and Mini-ACE Plus termi-
nals, and are software compatible with the original ACE series.
The Enhanced Mini-ACE provides complete multiprotocol sup-
port of MIL-STD-1553A/B/McAir and STANAG 3838. All versions
integrate dual transceiver; along with protocol, host interface,
memory management logic; and a minimum of 4K words of
RAM. In addition, the BU-61864 and BU-61865 BC/RT/MT ter-
minals include 64K words of internal RAM, with built-in parity
checking.
The Enhanced Mini-ACEs include a 5V, voltage source trans-
ceiver for improved line driving capability, with options for MIL-
STD-1760 and McAir compatibility. As a means of reducing
power consumption, there are versions for which the logic is
powered by 3.3V, rather than 5V. To provide further flexibility, the
Enhanced Mini-ACE may operate with a choice of 10, 12, 16, or
20 MHz clock inputs.
One of the new salient features of the Enhanced Mini-ACE is its
Enhanced bus controller architecture. The Enhanced BC's high-
ly autonomous message sequence control engine provides a
means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the pur-
pose of performing messaging to the host processor, the
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
A second major new feature of the Enhanced Mini-ACE is the
incorporation of a fully autonomous built-in self-test. This test
provides comprehensive testing of the internal protocol logic. A
separate test verifies the operation of the internal RAM. Since
the self-tests are fully autonomous, they eliminate the need for
the host to write and read stimulus and response vectors.
The Enhanced Mini-ACE RT offers the same choices of single,
double, and circular buffering for individual subaddresses as
ACE and Mini-ACE (Plus). New enhancements to the RT archi-
tecture include a global circular buffering option for multiple (or
all) receive subaddresses, a 50% rollover interrupt for circular
buffers, an interrupt status queue for logging up to 32 interrupt
events, and an option to automatically initialize to RT mode with
the Busy bit set. The interrupt status queue and 50% rollover
interrupt features are also included as improvements to the
Enhanced Mini-ACE's Monitor architecture.
To minimize board space and "glue" logic, the Enhanced Mini-
ACE terminals provide the same wide choice of host interface
configurations as the ACE and Mini-ACE (Plus). This includes
support of interfaces to 16-bit or 8-bit processors, memory or
port type interfaces, and multiplexed or non-multiplexed
(2)
Impedance parameters are specified directly between pins
TX/RX_A(B) and TX/RX_A(B) of the Enhanced Mini-ACE hybrid.
(3)
It is assumed that all power and ground inputs to the hybrid are con-
nected.
(4)
The specifications are applicable for both unpowered and powered
conditions.
(5)
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6)
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7)
Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8)
Typical value for minimum intermessage gap time. Under software
control, this may be lengthened to 65,535 ms - message time, in
increments of 1 s. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-
message gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6 clock
cycles. Since there are 7 internal transfers during SOM, and 5 dur-
ing EOM, this could theoretically lengthen the intermessage gap by
up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz clock, 6.0 s
with a 12 MHz clock, 4.5 s with a 16 MHz clock, or 3.6 s with a
20 MHz clock.
(9)
For Enhanced BC mode, the typical value for intermessage gap
time is approximately 10 clock cycles longer than for the non-
enhanced BC mode. That is, an addition of 1.0 s at 10 MHz, 833
ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
(10) Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) External 10 F Tantalum and 0.1 F capacitors should be located
as close as possible to Pins 20 and 72, and a 0.1 F at pin 37. For
BU-61864 and BU-61865, there should also be a 0.1 F at pin 26.
(13) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub connection.
(14) Power dissipation specifications assume a transformer coupled
configuration with external dissipation (while transmitting) of:
0.14 watts for the active isolation transformer,
0.08 watts for the active bus coupling transformer,
0.45 watts for each of the two bus isolation resistors and
0.15 watts for each of the two bus termination resistors.
NOTES: (Cont’d)
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