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參數(shù)資料

型號(hào)：	BU-61845G3-160W
廠商：	DATA DEVICE CORP
元件分類(lèi)：	微控制器/微處理器
英文描述：	2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝：	25.40 X 25.40 MM, 2.54 MM HEIGHT, CERAMIC, QFP-72
文件頁(yè)數(shù)：	7/60頁(yè)
文件大小：	457K
代理商：	BU-61845G3-160W

Data Device Corporation

www.ddc-web.com

BU-6174X/6184X/6186X

F-10/02-300

BC Time Remaining to Next Message Register: Provides a

read-only indication of the time remaining before the start of the

next message in a BC frame. In the enhanced BC mode, this

timer may also be used for the BC message sequence control

processor's Delay (DLY) instruction, or for minor or major frame

control. The resolution of this register is 1 s/LSB.

BC Frame Time/ RT Last Command /MT Trigger Word Register:

In BC mode, this register is used to program the BC frame time,

for use in the frame auto-repeat mode. The resolution of this reg-

ister is 100 s/LS, with a range up to 6.55 seconds. In RT mode,

this register stores the current (or most previous) 1553

Command Word processed by the Enhanced Mini-ACE RT. In

the Word Monitor mode, this register is used to specify a 16-bit

Trigger (Command) Word. The Trigger Word may be used to start

or stop the monitor, or to generate interrupts.

BC Initial Instruction List Pointer Register: Enables the host

to assign the starting address for the enhanced BC Instruction

List.

RT Status Word Register and BIT Word Registers: Provide

read-only indications of the RT Status and BIT Words.

Configuration Registers #6 and #7: Used to enable the

Enhanced Mini-ACE/-ACE features that extend beyond the

architecture of the ACE/Mini-ACE (Plus). These include the

Enhanced BC mode; RT Global Circular Buffer (including buffer

size); the RT/MT Interrupt Status Queue, including valid/invalid

message filtering; enabling a software-assigned RT address;

clock frequency selection; a base address for the "non-data" por-

tion of Enhanced Mini-ACE/-ACE memory; LSB filtering for the

Synchronize (with data) time tag operations; and enabling a

watchdog timer for the Enhanced BC message sequence control

engine.

BC Condition Code Register: Used to enable the host proces-

sor to read the current value of the Enhanced BC Message

Sequence Control Engine's condition flags.

BC General Purpose Flag Register: Allows the host processor

to be able to set, clear, or toggle any of the Enhanced BC

Message Sequence Control Engine's General Purpose condition

flags.

BIT Test Status Register: Used to provide read-only access to

the status of the protocol and RAM built-in self-tests (BIT).

BC General Purpose Queue Pointer: Provides a means for ini-

tializing the pointer for the General Purpose Queue, for the

Enhanced BC mode. In addition, this register enables the host to

determine the current location of the General Purpose Queue

pointer, which is incremented internally by the Enhanced BC

message sequence control engine.

RT/MT Interrupt Status Queue Pointer: Provides a means for

initializing the pointer for the Interrupt Status Queue, for RT, MT,

and RT/MT modes. In addition, this register enables the host to

determine the current location of the Interrupt Status Queue

pointer, which is incremented by the RT/MT message processor.

BC Control Word. The BC Control Word contains bits that select

the active bus and message format, enable off-line self-test,

masking of Status Word bits, enable retries and interrupts, and

specify MIL-STD-1553A or -1553B error handling. In RT mode,

this register allows host access to the current or most recent

Subaddress Control Word. The Subaddress Control Word is

used to select the memory management scheme and enable

interrupts for the current message.

Time Tag Register: Maintains the value of a real-time clock. The

resolution of this register is programmable from among 2, 4, 8,

16, 32, and 64 s/LSB. The Start-of-Message (SOM) and End-

of-Message (EOM) sequences in BC, RT, and Message Monitor

modes cause a write of the current value of the Time Tag

Interrupt Status Registers #1 and #2: Allow the host processor

to determine the cause of an interrupt request by means of one

or two read accesses. The interrupt events of the two Interrupt

Status Registers are mapped to correspond to the respective bit

positions in the two Interrupt Mask Registers. Interrupt Status

cate an interrupt event from Interrupt Status Register #1.

Configuration Registers #3, #4, and #5: Used to enable many

of the Enhanced Mini-ACE's/-ACE’s advanced features that

were implemented by the prior generation products, the ACE and

Mini-ACE (Plus). For BC, RT, and MT modes, use of the

Enhanced Mode enables the various read-only bits in

Configuration Register #1. For BC mode, Enhanced Mode fea-

tures include the expanded BC Control Word and BC Block

Status Word, additional Stop-On-Error and Stop-On-Status Set

functions, frame auto-repeat, programmable intermessage gap

times, automatic retries, expanded Status Word Masking, and

the capability to generate interrupts following the completion of

any selected message. For RT mode, the Enhanced Mode fea-

tures include the expanded RT Block Status Word, combined

RT/Selective Message Monitor mode, automatic setting of the

TERMINAL FLAG Status Word bit following a loop test failure;

the double buffering scheme for individual receive (broadcast)

subaddresses, and the alternate (fully software programmable)

RT Status Word. For MT mode, use of the Enhanced Mode

enables the Selective Message Monitor, the combined

RT/Selective Monitor modes, and the monitor triggering capabil-

ity.

RT/Monitor Data Stack Address Register: Provides a

read/writable indication of the last data word stored for RT or

Monitor modes.

BC Frame Time Remaining Register: Provides a read-only

indication of the time remaining in the current BC frame. In the

enhanced BC mode, this timer may be used for minor or major

frame control, or as a watchdog timer for the BC message

sequence control processor. The resolution of this register is

100 s/LSB.

相關(guān)PDF資料	PDF描述
BU-61845G3-160Z	2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61845G3-162K	2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61845G3-162S	2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61845G3-170W	2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
BU-61845G3-170Y	2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
BU-61845G4-100	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:Telecommunication IC
BU-61845G4-110	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:Telecommunication IC
BU-61860B3NEW	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:MIL-STD-1553 Components \|μ-ACE (Micro-ACE?)
BU-61864	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:MIL-STD-1553 Components \|Enhanced Mini-ACE?
BU-61864F3-100	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:Telecommunication IC

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