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參數(shù)資料
| 型號： | BU-61843G4-780L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 25.40 X 25.40 MM, 3.94 MM HEIGHT, CERAMIC, FP-72 |
| 文件頁數(shù)： | 42/60頁 |
| 文件大?。?/td> | 700K |
| 代理商： | BU-61843G4-780L |
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47
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
Rev. C
POL_SEL (I) /
DTACK (O)
29
Data Transfer Acknowledge or Polarity Select. In 16-bit buffered mode, if POL_SEL is connected to logic
"1", RD/WR should be asserted high (logic "1") for a read operation and low (logic "0") for a write opera-
tion. In 16-bit buffered mode, if POL_SEL is connected to logic "0", RD/WR should be asserted low (logic
"0") for a read operation and high (logic "1") for a write operation.
In 8-bit buffered mode (TRANSPARENT/ BUFFERED = “0" and 16/8 = "0"), POL_SEL input signal used to
control the logic sense of the MSB/LSB signal. If POL_SEL is connected to logic “0", MSB/LSB should be
asserted low (logic "0") to indicate the transfer of the least significant byte and high (logic "1") to indicate
the transfer of the most significant byte. If POL_SEL is connected to logic “1", MSB/LSB should be assert-
ed high (logic "1") to indicate the transfer of the least significant byte and low (logic "0") to indicate the
transfer of the most significant byte.
In transparent mode, active low output signal (DTACK) used to indicate acceptance of the processor/RAM
interface bus in response to a data transfer grant (DTGRT). The Enhanced Mini-ACE's RAM transfers over
A15-A0 and D15-D0 will be framed by the time that DTACK is asserted low.
TRIG_SEL (I) /
MEMENA_IN (I)
28
Memory Enable or Trigger Select input. In 8-bit buffered mode, input signal (TRIG-SEL) used to select the
order in which byte pairs are transferred to or from the Enhanced MINI-ACE by the host processor. In the
8-bit buffered mode, TRIG_SEL should be asserted high (logic 1) if the byte order for both read operations
and write operations is MSB followed by LSB. TRIG_SEL should be asserted low (logic 0) if the byte order
for both read operations and write operations is LSB followed by MSB.
In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS) input to the Enhanced Mini-
ACE's internal shared RAM. If only internal RAM is used, should be connected directly to the output of a gate that
is OR'ing the DTACK and IOEN output signals.
MEM / REG(I)
1
Memory/Register. Generally connected to either a CPU address line or address decoder output. Selects
between memory access (MEM/REG = "1") or register access (MEM/REG = "0").
SSFLAG (I) /
EXT_TRIG(I)
32
Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input. In RT mode, if this input is asserted
low, the Subsystem Flag bit will be set in the ENHANCED MINI-ACE's RT Status Word. If the SSFLAG
input is logic "0" while bit 8 of Configuration Register #1 has been programmed to logic "1" (cleared), the
Subsystem Flag RT Status Word bit will become logic "1," but bit 8 of Configuration Register #1, SSFLAG,
will return logic "1" when read. That is, the sense on the SSFLAG input has no effect on the SUBSYSTEM
FLAG register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC mode, if the exter-
nal BC Start option is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will
issue a BC Start command, starting execution of the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the
Enhanced Mini-ACE BC will wait for a low-to-high transition on EXT_TRIG before proceeding to the next
instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration Register #1), a low to
high transition on this input will initiate a monitor start.
This input has no effect in Message Monitor mode.
TABLE 51. PROCESSOR INTERFACE CONTROL (CONT.)
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
PIN
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