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    參數(shù)資料
    型號: BU-61703F3-170K
    廠商: DATA DEVICE CORP
    元件分類: 微控制器/微處理器
    英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
    封裝: CERAMIC, QFP-72
    文件頁數(shù): 27/54頁
    文件大小: 576K
    代理商: BU-61703F3-170K
    33
    Data Device Corporation
    www.ddc-web.com
    BU-61703/61705
    D1 web-09/02-0
    P.C. BOARD LAYOUT GUIDELINES
    GROUND PLANES
    As is the rule in all high-speed digital circuits, it is good practice
    to use ground and power supply planes under the SSRT hybrid
    as well as the associated digital components.
    The reason for not using supply or ground planes under the ana-
    log signal traces is that the effect of the distributed capacitance
    will be to lower the input impedance of the terminal, as seen from
    the 1553 bus. MIL-STD-1553 requires a minimum input imped-
    ance of 2000 ohms for direct coupled terminals and 1000 ohms
    for transformer (stub) coupled terminals. If there are ground
    planes under the analog bus signal traces, it is likely that the ter-
    minal will not meet this requirement.
    POWER AND GROUND DISTRIBUTION
    Another important consideration is power and ground distribu-
    tion. Refer to FIGURE 15. For the SSRT hybrid/transformer com-
    bination, the high current path when the SSRT is transmitting will
    be from the +5 volt power supply, through the transmitter output
    stage, through one leg of the isolation transformer to the trans-
    former center tap. It is important to realize that the high current
    return path is through the transformer center tap and not through
    the SSRT GROUND pins.
    Another important layout consideration is to minimize the power
    supply distribution impedance along this path. Any resistance will
    result in voltage drops for the power supply input voltage, and
    can ultimately lower the transmitter output voltage, possibly
    below the minimum level required by MIL-STD-1553 or
    MIL-STD-1760.
    However, it is very important that there be NO ground
    and/or power supply planes underneath the analog bus
    signal traces. This applies to the TX/RX signals running
    between the SSRT and the isolation transformers as well
    as the traces between the transformers to any connectors
    or cables leaving the board.
    FIGURE 15. POWER - GROUND DISTRIBUTION
    LOGIC
    RX
    TRANSCEIVER
    TX
    HIGH LEVEL
    CURRENTS
    LOW LEVEL
    CURRENTS
    LOW / MEDIUM
    LEVEL
    CURRENTS
    LOGIC
    GND
    GND A/B
    LOGIC
    +5 V A/B
    +5 V
    or
    +3.3 V
    SSRT
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