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| 型號： | BU-61583D1-500L |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| 封裝： | CERAMIC, DIP-70 |
| 文件頁數(shù)： | 16/48頁 |
| 文件大?。?/td> | 378K |
| 代理商： | BU-61583D1-500L |
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Data Device Corporation
www.ddc-web.com
BU-61582
G-08/02-250
PROCESSOR AND MEMORY INTERFACE
The SP’ACE terminals provide much flexibility for interfacing to a
host processor and optional external memory. FIGURE 1 shows
that there are 14 control signals, 6 of which are dual purpose, for
the processor/memory interface. FIGURES 9 through 14 illus-
trate six of the configurations that may be used for interfacing the
BU-61582 to a host processor bus. The various possible config-
urations serve to reduce to an absolute minimum the amount of
glue logic required to interface to 8-, 16-, and 32-bit processor
buses. Also included are features to facilitate interfacing to
processors that do not have a “wait state” type of handshake
acknowledgment. Finally, the SP’ACE supports a reliable inter-
face to an external dual port RAM. This type of interface mini-
mizes the portion of the available processor bandwidth required
to access the 1553 RAM.
The 16-bit buffered mode (FIGURE 9) is the most common con-
figuration used. It provides a direct, shared RAM interface to a
16-bit or 32-bit microprocessor. In this mode, the SP’ACE’s inter-
nal address and data buffers provide the necessary isolation
between the host processor’s address and data buses and the
corresponding internal memory buses. In the buffered mode, the
1553 shared RAM address space limit is the BU-61582’s 16K
words of internal RAM. The 16-bit buffered mode provides a pair
of pin-programmable options:
(1) The logic sense of the RD/WR control input is selectable by
the POLARITY_SEL input; for example, write when RD/WR is
low for Motorola 680X0 processors; write when RD/WR is high
for the Intel i960 series microprocessors.
(2) By strapping the input signal ZERO WAIT to logic “1”, the
SP’ACE terminals may interface to processors that have an
acknowledge type of handshake input to accommodate hard-
ware controlled wait states; most current processor chips have
such an input. In this case, the BU-61582 will assert its READY
output low only after it has latched WRITE data internally or has
presented READ data on D15-D0.
By strapping ZERO WAIT to logic “0”, it is possible to easily inter-
face the BU-61582 to processors that do not have an acknowl-
edge type of handshake input. An example of such a processor
is Analog Device’s ADSP2101 DSP chip. In this configuration,
the processor can clear its strobe output before the completion
of access to the BU-61582 internal RAM or register. In this case,
READY goes high following the rising edge of STRBD and will
stay high until completion of the transfer. READY will normally be
low when ZERO WAIT is low.
Similar to the 16-bit buffered mode, the 16-bit transparent mode
(FIGURE 10) supports a shared RAM interface to a host CPU.
The transparent mode offers the advantage of allowing the buffer
RAM size to be expanded to up to 64K words, using external
RAM. A disadvantage of the transparent mode is that it requires
external address and data buffers to isolate the processor buses
from the memory/BU-61582 buses.
A modified version of the transparent mode involves the use of
dual port RAM, rather than conventional static RAM. Refer to
FIGURE 11. This allows the host to access RAM very quickly, the
only limitation being the access time of the dual port RAM. This
configuration eliminates the BU-61582 arbitration delays for
memory accesses. The worst case delay time occurs only during
a simultaneous access by the host and the BU-61582 1553 logic
to the same memory address. In general, this will occur very
rarely and the SP’ACE limits the delay to approximately 250 ns.
FIGURE 12 illustrates the connections for the 16-bit Direct
Memory Access (DMA) mode. In this configuration the host
processor, rather than the SP’ACE terminal, arbitrates the use of
the address and data buses. The arbitration involves the two
DMA output signals Request (DTGRT) and Acknowledge
(DTACK) and the input signal Grant (DTGRT). The DMA interface
allows the SP’ACE components to interface to large amounts of
system RAM while eliminating the need for external buffers. For
system address spaces larger than 64K words, it is necessary
for the host processor to provide a page register for the upper
address bits (above A15) when the BU-61582 accesses the
RAM (while asserting (DTACK) low).
The internal RAM is accessible through the standard SP’ACE
interface (SELECT, STRBD, READYD, etc). The host CPU may
access external RAM by the SP’ACE’s arbitration logic and out-
put control signals, as illustrated in FIGURE 12. Alternatively,
control of the RAM may be shared by both the host processor
and the SP’ACE, as illustrated in FIGURE 13. The latter requires
the use of external logic, but allows the processor to access the
RAM directly at the full access speed of the RAM, rather than
waiting for the SP’ACE handshake acknowledge output READY.
FIGURE 14 illustrates the 8-bit buffered mode. This interface
allows a direct connection to 8-bit microprocessors and 8-bit
microcontrollers. As in the 16-bit buffered configuration, the
buffer RAM limit is the BU-61582’s 16K words of internal RAM.
In the 8-bit mode, the host CPU accesses the BU-61582’s inter-
nal registers and RAM by a pair of 8-bit registers embedded in
the SP’ACE interface. The 8-bit interface may be further config-
ured by three strappable inputs: ZEROWAIT POLARITY_SEL,
and TRIGGER_SEL. By connecting ZEROWAIT to logic “0”, the
BU-61582 may be interfaced with minimal “glue” logic to 8-bit
microcontrollers, such as the Intel 8051 series, that do not have
an Acknowledge type of handshake input. The programmable
inputs POLARITY_SEL and TRIGGER_SEL allow the BU-61582
to accommodate the different byte ordering conventions and
“A0” logic sense utilized by different 8-bit processor families.
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