
32
Data Device Corporation
www.ddc-web.com
BU-61582
G-08/02-250
CLOCK IN
VALID
t7
t3
t8
t11
t13
t15
VALID
t10
t4
t9
t12
t19
;
;;
;
VALID
t16
t17
SELECT
(Note 2,7)
(Note 2)
(Note 3,4,7)
(Note 4,5)
STRBD
MEM/REG
RD/WR
IOEN
(Note 2,6)
(Note 6)
READYD
A15-A0
(Note 7, 8)
D15-D0
(Note 6)
;;
;
;;
;;;
;;
t5
t1
t2
t6
t14
t18
FIGURE 16. CPU READING RAM (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)