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25
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
H1 web-09/02-0
FIGURE 12. 16-BIT DIRECT MEMORY ACCESS (DMA) MODE
HOST
ACE
55
55
8
7
5
4
1
2
3
CH. A
TX/RXA
55
55
8
7
5
4
1
2
3
CH. B
TX/RXB
RTAD4-RTAD0
RT
ADDRESS,
PARITY
RTADP
D15-D0
+5V
+15V
CLK IN
16 MHz
CLOCK
OSCILLATOR
ADDRESS
DECODER
SELECT
MEM/REG
RESET
+5V
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
CPU D15-D0
RAM
64K x 16 MAX
WR
OE
CS
MEMWR
MEMOE
RD/WR
DTREQ
DTGRT
DTACK
A15-A0
ADDRESS
DECODER
MEMENA-IN
EN
MEMENA-OUT
TRANSPARENT/BUFFERED
+5V
STRBD
READYD
TAG_CLK
CPU STROBE
CPU ACKNOWLEDGE
CPU A15-A0