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參數(shù)資料
| 型號(hào)： | BU-61559D1-230Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| 封裝： | 45.70 X 53.30 MM, 5.30 MM HEIGHT, CERAMIC, DDIP-78 |
| 文件頁(yè)數(shù)： | 16/32頁(yè) |
| 文件大小： | 438K |
| 代理商： | BU-61559D1-230Z |
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23
Data Device Corporation
www.ddc-web.com
BU-61559 Series
E-03/06-0
FIGURE 22. CPU READING RAM (SHOWN FOR BUFFERED MODE)
Notes for FIGURE 22:
1. For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ/16/8 must be connected to logic "1". The inputs TRIG-
GER_SEL and MSB/LSB may be connected to either +5V or ground.
2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT STRBD is sampled low (satisfying t1) and the BU-61559's protocol/memory management
logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer cycle. After IOEN goes low, SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for register access.
4. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0", RD/WR must be asserted low to read.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. Timing for A15-A0, MEM/REG and SELECT assumes ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional details.
8. Internal RAM is accessed by A11 through A0 (A13 through A0 for 61585, 61586, 61582 and 61583, A15 through A0 for 61688 and 61689). Registers are accessed by A4 through A0.
9. The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0 become latched internally.
10. Setup time given for use in worst case timing calculations. None of the input signals are required to be synchronized to the system clock. When SELECT and STRBD do not meet the setup time
of t1, but occur during the setup window of an internal flip-flop, an additional clock cycle will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge
that latches the Address (A15-A0). When this occurs, the pulse width of IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold time (t10) must be increased be one
clock cycle.
t3
MEM/REG and RD/WR setup time following SELECT and STRBD low (Notes 3,4,5,7)
t2
107.5
2.8
ns
30
ns
35
ns
10
ns
MIN
BU-61559
DESCRIPTION
REF
CPU READING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
TYP MAX
UNIT
SELECT and STRBD low to IOEN low (uncontended access) (Notes 2,6)
SELECT and STRBD low to IOEN low (contended access) (Notes 2,6)
t1
20
ns
SELECT and STRBD low setup time prior to clock rising edge (Note 2,10)
t4
Address valid setup time following SELECT and STRBD low.
t5
CLOCK IN rising edge delay to IOEN falling edge (Note 6)
0
ns
10
ns
t6
SELECT hold time following IOEN falling (Note 2)
t7
MEM/REG, RD/WR setup time prior to CLOCK IN falling edge (Notes 3,4,5,7)
30
ns
30
ns
t8
MEM/REG, RD/WR hold time following CLOCK IN falling edge (Notes 3,4,5,7)
t9
Address valid setup time prior to CLOCK IN rising edge (Notes 7,8,9)
30
ns
170
187.5
205
ns
t10
Address hold time following CLOCK IN rising edge (Notes 7,8,9,10)
t11
IOEN falling delay to READYD falling (reading RAM) (Notes 6,10)
IOEN falling delay to READYD falling (reading registers) (Notes 6,10)
33
ns
t12
Output Data valid prior to READYD falling (Note 6)
35
ns
∞
ns
t13
CLOCK IN rising edge delay to READYD falling (Note 6)
t14
READYD falling to STRBD rising release time.
30
ns
0
ns
t15
STRBD rising edge delay to IOEN rising edge and READYD rising edge (Note 6)
t16
Output Data hold time following STRBD rising edge.
40
ns
t17
STRBD rising delay to output Data tri-state
0
ns
60
ns
t18
STRBD high hold time from READYD rising
t19
CLOCK IN rising edge delay to Output data valid
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| BU-61580 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |ACE |
| BU-61580G1-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580G1-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580G1-120 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580G1-200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
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