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參數(shù)資料
| 型號： | BT162827ADGG |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 20-bit buffer/line driver, non-inverting,with 30ohm termination resistors (3-State) |
| 中文描述： | ABT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 78K |
| 代理商： | BT162827ADGG |
Philips Semiconductors
Product specification
74ABT162827A
74ABTH162827A
20-bit buffer/line driver, non-inverting,
with 30 termination resistors (3-State)
1998 Feb 27
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
MAX
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
t/
v
DC supply voltage
4.5
5.5
V
Input voltage
0
V
CC
V
High-level input voltage
2.0
V
Low-level Input voltage
0.8
V
High-level output current
–32
mA
Low-level output current
12
mA
Input transition rise or fall rate
0
10
ns/V
T
amb
Operating free-air temperature range
–40
+85
°
C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25
°
C
T
amb
= -40
°
C
°
C
MIN
UNIT
MIN
TYP
–0.9
3.1
3.6
2.7
MAX
–1.2
MAX
–1.2
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= -18mA
V
CC
= 4.5V; I
OH
= -3mA; V
I
= V
IL
or V
IH
V
CC
= 5.0V; I
OH
= -3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= -32mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= 8mA; V
l
= V
IL
or V
IN
V
CC
= 4.5V; I
OL
= 12mA; V
I
= V
IL
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 5.5V; V
I
= 5.5V
V
V
V
V
V
V
μ
A
μ
A
2.5
3.0
2.0
2.5
3.0
2.0
V
OH
High-level output voltage
V
OL
Low level output voltage
Low-level output voltage
0.65
0.80
±
1.0
1
0.65
0.80
±
1.0
1
I
I
Input leakage current
±
0.01
0.01
I
Input leakage current
74ABTH162827A
V
CC
= 5.5V; V
I
= V
CC
or GND
Control
pins
±
0.01
±
1
±
1
μ
A
I
V
CC
= 5.5V; V
I
= V
CC
V
CC
= 5.5V; V
I
= 0
V
CC
= 4.5V; V
I
= 0.8V
V
CC
= 4.5V; V
I
= 2.0V
V
CC
= 5.5V; V
I
= 0 to 5.5V
V
CC
= 0.0V; V
O
= 4.5V; V
I
= 0V or 5.5V
V
CC
= 2.1V; V
= 0.5V; V
I
= GND or V
CC
;
V
OE
= Don’t care
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
Data pins
4
0.01
–1
1
–3
1
–5
μ
A
μ
A
Bus H ld
74ABTH162827A
t A i
t
5
35
–75
±
800
35
–75
I
HOLD
μ
A
I
OFF
Power-off leakage current
Power-up/down 3-State
output current
3
3-State output High current
3-State output Low current
Output High leakage
current
Output current
1
±
5.0
±
100
±
100
μ
A
I
PU
/I
PD
±
5.0
±
50
±
50
μ
A
I
OZH
I
OZL
1.0
–1.0
10
–10
10
–10
μ
A
μ
A
I
CEX
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
1.0
50
50
μ
A
I
O
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or
V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3-State;
V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
–50
–70
–180
–50
–180
mA
I
CCH
0.5
1
1
mA
I
CCL
Quiescent supply current
9
19
19
mA
I
CCZ
0.5
1
1
mA
I
CC
Additional supply current
per input pin
2
0.2
1
1
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. From V
CC
= 2.1V to V
CC
= 5V
±
10% a
transition time of up to 100
μ
sec is permitted.
4. Unused pins at V
CC
or GND.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
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