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參數(shù)資料
| 型號(hào)： | BSP120 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 小信號(hào)晶體管 |
| 英文描述： | N-channel enhancement mode vertical D-MOS transistor |
| 中文描述： | 250 mA, 200 V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 65K |
| 代理商： | BSP120 |
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP120
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
THERMAL RESISTANCE
Note
1.
Device mounted on an epoxy printed-circuit board 40 mm
×
40 mm
×
1.5 mm; mounting pad for the drain lead
min. 6 cm
2
.
CHARACTERISTICS
T
j
= 25
°
C unless otherwise specified
Drain-source voltage
Gate-source voltage (open drain)
Drain current (DC)
Drain current (peak)
Total power dissipation up to T
amb
= 25
°
C (note 1)
Storage temperature range
Junction temperature
V
DS
±
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
max.
max.
max.
max.
max.
200 V
20 V
250 mA
800 mA
1.5 W
65 to + 150
°
C
max.
150
°
C
From junction to ambient (note 1)
R
th j-a
=
83.3 K/W
Drain-source breakdown voltage
I
D
= 10
μ
A; V
GS
= 0
Drain-source leakage current
V
DS
=160 V; V
GS
= 0
Gate-source leakage current
V
GS
= 20 V; V
DS
= 0
Drain-source ON-resistance (see Fig.4)
I
D
= 250 mA; V
GS
= 10 V
V
(BR)DSS
min.
200 V
I
DSS
max.
1.0
μ
A
I
GSS
max.
100 nA
typ.
max.
7
12
R
DS(on)
Gate threshold voltage
I
D
= 1 mA; V
GS
= V
DS
min.
max.
0.8
2.8
V
V
V
GS(th)
Transfer admittance
I
D
= 250 mA; V
DS
= 15 V
min.
typ.
125
250
mS
mS
Y
fs
Input capacitance at f = 1 MHz;
V
DS
= 10 V; V
GS
= 0
typ.
max.
45
65
pF
pF
C
iss
Output capacitance at f = 1 MHz;
V
DS
= 10 V; V
GS
= 0
typ.
max.
20
30
pF
pF
C
oss
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