
Ultra Low Power CMOS SRAM
256K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BS616UV4016
R0201-BS616UV4016
Revision
May.
1.6
2006
1
n
FEATURES
Wide V
CC
low operation voltage :
Ultra low power consumption :
V
CC
= 2.0V
V
CC
= 3.0V
High speed access time :
-10
Automatic power down when chip is deselected
Easy expansion with CE and OE options
I/O Configuration x8/x16 selectable by LB and UB pin.
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
n
POWER CONSUMPTION
C-grade : 1.8V ~ 3.6V
I-grade : 1.9V ~ 3.6V
Operation current : 12mA (Max.) at 100ns
1mA (Max.) at 1MHz
Standby current :
0.1uA (Typ.) at 25
O
C
Operation current : 15mA (Max.) at 100ns
2mA (Max.) at 1MHz
Standby current :
0.25uA (Typ.) at 25
O
C
100ns (Max.)
n
DESCRIPTION
The BS616UV4016 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 262,144 by 16 bits and
operates form a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.1uA at 2.0V/25
O
C and maximum access time of 100ns at
85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BS616UV4016 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616UV4016 is available in DICE form, JEDEC standard
44-pin TSOP II and 48-ball BGA package.
POWER DISSIPATION
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
V
CC
=3.0V
V
CC
=2.0V
PRODUCT
FAMILY
OPERATING
TEMPERATURE
V
CC
=3.0V
V
CC
=2.0V
1MHz
f
Max.
1MHz
f
Max.
PKG TYPE
BS616UV4016DC
DICE
BS616UV4016AC
BS616UV4016EC
BGA-48-0608
TSOP II-44
Commercial
+0
C to +70
O
C
2.0uA
1.0uA
1.5mA
13mA
0.8mA
10mA
BS616UV4016AI
BS616UV4016EI
BGA-48-0608
TSOP II-44
Industrial
-40
O
C to +85
O
C
4.0uA
2.0uA
2.0mA
15mA
1.0mA
12mA
n
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc.
reserves the right to modify document contents without notice.
n
BLOCK DIAGRAM
A4
A3
A2
A1
A0
DCE
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
DQ7
WE
A17
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616UV4016EC
BS616UV4016EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A7
OE
UB
LB
DQ14
DQ13
DQ12
VSS
DQ11
DQ9
DQ8
NC
A8
A10
A11
A12
G
H
F
E
D
C
B
A
1
2
3
4
5
6
A9
A11
A10
NC
A12
A14
A13
A15
WE
D13
D5
D7
D6
A17
A16
A7
VSS
VCC
D12
D11
D4
D3
NC
A5
OE
A3
A0
A6
A4
A1
A2
NC
UB
D10
D1
CE
D2
D0
48-ball BGA top view
LB
D8
D9
VSS
VCC
D14
D15
NC
NC
A8
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 4096
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
A14
A16
A0 A1
Data
Input
Control
DQ0
.
.
.
.
.
.
DQ15
A12
A11
A10
A9
A8
A5
A6
A7
A4
A3
16
16
16
16
8
256
4096
1024
10
A13
Data
Buffer
A15
CE
WE
OE
UB
LB
V
CC
V
SS
A2
.
.
.
.
.
.
A17