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參數(shù)資料
| 型號： | BRF1A |
| 廠商： | Lineage Power |
| 英文描述： | Quad Differential Receivers(四差分接收器) |
| 中文描述： | 四路差分接收器（四差分接收器） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 306K |
| 代理商： | BRF1A |
Lucent Technologies Inc.
7
Data Sheet
March 1999
BRF1A, BRF2A, BRR1A, BRS2A, and BRT1A
Quad Differential Receivers
ESD Failure Models
Lucent employs two models for ESD events that can
cause device damage or failure.
1. A human-body model (HBM) that is used by most of
the industry for ESD-susceptibility testing and pro-
tection-design evaluation. ESD voltage thresholds
are dependent on the critical parameters used to
define the model. A standard HBM (resistance =
1500
, capacitance = 100 pF) is widely used and,
therefore, can be used for comparison purposes.
2. A charged-device model (CDM), which many believe
is the better simulator of electronics manufacturing
exposure.
Tables 5 and 6 illustrates the role these two models play
in the overall prevention of ESD damage. HBM ESD
testing is intended to simulate an ESD event from a
charged person. The CDM ESD testing simulates
charging and discharging events that occur in produc-
tion equipment and processes, e.g., an integrated cir-
cuit sliding down a shipping tube.
The HBM ESD threshold voltage presented here was
obtained by using these circuit parameters.
Table 5. Typical ESD Thresholds for Data
Transmission Receivers
Table 6. ESD Damage Protection
Device
HBM Threshold
Differential
Inputs
>
800
CDM
Threshold
Others
BRF1A,
BRR1A,
BRT1A
BRF2A,
BRS2A
>
2000
>
1000
>
2000
>
2000
>
2000
ESD Threat Controls
Personnel
Wrist straps
ESD shoes
Antistatic flooring
Human-body
model (HBM)
Processes
Static-dissipative
materials
Air ionization
Charged-device
model (CDM)
Control
Model
Latch-Up
Latch-up evaluation has been performed on the data transmission receivers. Latch-up testing determines if power-
supply current exceeds the specified maximum due to the application of a stress to the device under test. A device
is considered susceptible to latch-up if the power supply current exceeds the maximum level and remains at that
level after the stress is removed.
Lucent performs latch-up testing per an internal test method that is consistent with JEDEC Standard No. 17 (previ-
ously JC-40.2) “CMOS Latch-Up Standardized Test Procedure.”
Latch-up evaluation involves three separate stresses to evaluate latch-up susceptibility levels:
1. dc current stressing of input and output pins.
2. Power supply slew rate.
3. Power supply overvoltage.
Table 7. Latch-Up Test Criteria and Test Results
Based on the results in Table 7, the data transmission receivers pass the Lucent latch-up testing requirements
and are considered not susceptible to latch-up.
dc Current Stress
of I/O Pins
≥
150 mA
≥
250 mA
Power Supply
Slew Rate
≤
1
μs
≤
100 ns
Power Supply
Overvoltage
≥
1.75 x Vmax
≥
2.25 x Vmax
Data Transmission
Receiver ICs
Minimum Criteria
Test Results
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相關代理商/技術參數(shù) |
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| BRF1A16E | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A |
| BRF1A16E-TR | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A |
| BRF1A16G | 制造商:AGERE 功能描述: |
| BRF1A16G-TR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:LSI Corporation 功能描述: |
| BRF1A16NB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Quad Differential Receivers BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A |
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