
4
Memory ICs
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
(2) Operation timing characteristics
(unless otherwise noted, Ta = – 40 to + 85°C, V
CC
 = 5V ± 10%)
Parameter
Symbol
Min.
Typ.
Max.
Unit
f
SK
—
—
1
MHz
t
SKH
450
—
—
ns
t
SKL
450
—
—
ns
t
CS
450
—
—
ns
t
CSS
50
—
—
ns
t
DIS
100
—
—
ns
t
CSH
0
—
—
ns
t
DIH
100
—
—
ns
t
PD1
—
—
500
ns
t
PD0
—
—
500
ns
t
SV
—
—
500
ns
t
DF
—
—
100
ns
—
—
10
ms
t
E / W
SK clock frequency
SK "H" time
SK "L" time
CS "L" time
CS setup time
DI setup time
CS hold time
DI hold time
Data "1" output delay time
Data "0" output delay time
Time from CS to output confirmation
Time from CS to output  High impedance
Write cycle time
Circuit operation
(1) Command mode
With these ICs, commands are not rec-
ognized or acted upon until the start bit
is received. The start bit is taken as the
first “1” that is received after the CS pin
rises. 
1 After setting of the read command
and input of the SK clock, data corre-
sponding to the specified address is
output, with data corresponding to up-
per addresses then output in se-
quence. (Auto increment function)
2 When the write or write all addresses command is executed, all data in the selected memory cell is erased auto-
matically, and the input data is written to the cell. 
3 These modes are optional modes. Please contact Rohm for information on operation timing.
1
10
1
00
1
01
D15 ~ D0
—
—
1
00
D15 ~ D0
—
—
—
1
00
1
11
1
00
0A6 ~ A0
11XXXXXX
0A6 ~ A0
01XXXXXX
00XXXXXX
0A6 ~ A0
10XXXXXX
Command
Read (READ)
1
Write enabled (WEN)
Write (WRITE)
2
Write all addresses (WRAL)
2
Write disabled (WDS)
Erase (ERASE)
3
Chip erase (ERAL)
3
Start
bit
Operating 
code
Address
Data
X: Either V
IH
 or V
IL