參數(shù)資料
型號: BR24E16FV
廠商: Rohm CO.,LTD.
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù): 9/12頁
文件大?。?/td> 298K
代理商: BR24E16FV
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
Memory Ics
BR24C16FJ /
BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
(9) Current read
BR24C08 / F / FJ / FV
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
1
1
R
/
W
A
C
K
A
C
K
DATA
S
T
O
P
0
0 A2 P1 P0
D7
D0
R
E
A
D
Fig.10
BR24C16 / F / FJ / FV
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
1
1
R
/
W
A
C
K
A
C
K
DATA
S
T
O
P
0
0 P2 P1 P0
D7
D0
R
E
A
D
Fig.11
BR24E16 / F / FJ / FV
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
1
1
R
/
W
A
C
K
A
C
K
DATA
S
T
O
P
0
0 A2 A1 A0
D7
D0
R
E
A
D
Fig.12
$
In case the previous operation is random or current read (which includes sequential read respectively), the
internal address counter is increased by one from the last accessed address (n). Thus current read outputs the
data of the next word address (n+1).
If the last command is byte or page write, the internal address counter stays at the last address (n). Thus current
read outputs the data of the word address (n).
If the master does not transfer the acknowledge but does generate a stop condition, the current address read
operation only provides s single byte of data.
At this point, this IC discontinues transmission.
$
When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (
μ
-COM), the
next word address data can be read.
[
All words all read enabled
]
(See Fig.16 to 18 for the sequential read cycles.)
$
This command is ended by inputting HIGH to the ACK signal after D0 and raising the SDA signal (stop
condition) by setting SCL to HIGH.
相關(guān)PDF資料
PDF描述
BR24L02FV-W 256x8 bit electrically erasable PROM
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