參數(shù)資料
型號: BR24C04FJ-W
廠商: Rohm CO.,LTD.
元件分類: DRAM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù): 11/13頁
文件大小: 341K
代理商: BR24C04FJ-W
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
(11) Sequential read cycle (For a current read)
BR24C01A-W / AF-W / AFJ-W / AFV-W
S
T
A
R
T
ADDRESS
SLAVE
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
R
E
A
D
DATA(n)
DATA(n
+
x)
SDA
LINE
1
1
0
0 A2 A1A0
D7
D7
D0
D0
S
T
O
P
Fig.16
BR24C02-W / F-W / FJ-W / FV-W
S
T
A
R
T
SLAVE
ADDRESS
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
R
E
A
D
DATA(n)
DATA(n
+
x)
SDA
LINE
1
1
0
0 A2 A1A0
D7
D7
D0
D0
S
T
O
P
Fig.17
BR24C04-W / F-W / FJ-W / FV-W
S
T
A
R
T
SLAVE
ADDRESS
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
R
E
A
D
DATA(n)
DATA(n
+
x)
SDA
LINE
1
1
0
0 A2 A1PS
D7
D7
D0
D0
S
T
O
P
Fig.18
When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (
μ
-COM), the next
word address data can be read.
[
All words can be read
]
This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop
condition) using the SCL signal HIGH.
Sequential reading can also be done with a random read.
相關(guān)PDF資料
PDF描述
BR24C04FV-W The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
BR24C01A-W The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
BR24C01AF-W The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
BR24C01AFV-W The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
BR24C02-W MOSFET N-CH 500V 36A TO-3P
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