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參數資料
| 型號： | BR24C01A-W |
| 廠商： | Rohm CO.,LTD. |
| 元件分類： | DRAM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個2 KB的EEPROM的國內256個8位每字舉辦的串行CMOS |
| 文件頁數： | 4/13頁 |
| 文件大?。?/td> | 341K |
| 代理商： | BR24C01A-W |
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
Memory ICs
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!
Timing charts
t
BUF
t
DH
t
PD
t
HIGH
t
HD
:
STA
t
LOW
t
F
t
R
SDA
(input)
SDA
SCL
START BIT
STOP BIT
SCL
SDA
·
Data is read on the rising edge of SCL.
·
Data is output in synchronization with the falling edge of SCL.
t
SU
: DAT
t
HD
: DAT
t
SU
: STO
t
HD
: STA
t
SU
: STA
(output)
Fig.1 Synchronized data input / output timing
ACK
D0
(n address)
t
WR
SDA
SCL
Start condition
Stop condition
Write data
Fig.2 Write cycle timing
!
Circuit operation
(1) Start condition (recognition of start bit)
Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from
HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and
SCL line, and no commands will be executed unless this condition is satisfied.
(See Fig.1 for the synchronized data input / output timing.)
(2) Stop condition (recognition of stop bit)
To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from
LOW to HIGH while SCL is HIGH. This enables commands to be completed.
(See Fig.1 for the synchronized data input / output timing.)
(3) Precautions concerning write commands
In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed.
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| BR24C01-DS6TP | 功能描述:電可擦除可編程只讀存儲器 I2C BUS; 4.5 to 5.5V 1Kbit; -40 to 85 C RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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